Can i get the trace memory acess from ArchC MIPS ISS?

[Francisco Carlos Silva Junior]

Is there a way to use the Mibench Benchmark package compiled for MIPS, available in the ArchC (http://archc.lsc.ic.unicamp.br/downloads/Bench/MipsMibench.tar.bz2), and run it on an architecture implemented in VHDL? When you run the Mibench in ArchC, you use the MIPS ISS (Instruction-Set Simulator) sending the input file as parameter, how can i emulate this behavior in VHDL? 

I am using a MIPS processor described in VHDL in order to obtain the memory acess trace from Mibench applications. Can i get the trace memory acess from ArchC MIPS ISS?

Francisco Carlos Silva Junior

Mestrando em Ciência da Computação na Universidade Federal do Piauí

[Rodolfo Azevedo]

Hi Francisco,

  You can get this trace in ArchC. This can be done through the MIPS model where you can get the instruction fetch through ac_behavior(instruction) and you can get all data load and stores through the respective instruction behavior, like ac_behavior(lw).

  In this way you can add printf statements to this file or send them to a specific output file as you wish. If you want to send to an output file, open the file in the ac_behavior(begin) and close the file in the ac_behavior(end).

  Alternatively, you can use a simple MIPS platform with one processor and memory and just write all memory access without the need to intercept the instructions. This access can even be collected from the TLM channel.

    Regards,

        Rodolfo

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Rodolfo Jardim de Azevedo
http://www.ic.unicamp.br/~rodolfo
IC - University of Campinas - UNICAMP