If the branch is taken in a pipeline, the PC is normally not updated until the end of which stage if there is no branch prediction

[Anshul Gupta]

If the branch is taken in a pipeline, the PC is normally not updated until the end of which stage if there is no branch prediction.

Assume the stages are Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM) and Write Back (WB).

If suppose I got a question like this then at what stage the branch instruction be executed?

Consider an instruction pipeline with five stages without any branch prediction: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX) and Operand Write (OW). The stage delays for IF, ID, OF, EX and OW are 5 nsec, 7 nsec, 10 nsec, 8 nsec and 6 nsec, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 nsec. A program consisting of 12 instructions I1, I2, …, I12 is executed in the pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time needed to complete the program is

[Smruti R. Sarangi]

The answer is there in Chapter 9. All the stage delays have to be the same.

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[Anshul Gupta]

Thank you for the clarification. 

Yours sincerely

Anshul Gupta