Fwd: FW: Please read: Critical Requirements. Employee Referrals/ Internal Applications Invited
Theiventhiran Murugan
From: Theiventhiran Murugan <Theiventhi...@synopsys.com>
Date: Tue, Jan 6, 2015 at 6:10 PM
Subject: FW: Please read: Critical Requirements. Employee Referrals/ Internal Applications Invited
To: "ursev...@gmail.com" <ursev...@gmail.com>
From: Akshat Chauhan [mailto:aks...@synopsys.com]
Sent: Tuesday, January 06, 2015 5:41 PM
To: all-in01-employees; all-in02-employees; all-in25-employees; all-in65-employees; all-in75-employees
Subject: [all-in01-employees] Please read: Critical Requirements. Employee Referrals/ Internal Applications Invited
Synopsys Employee Referral Program
Make a difference!
Dear Colleagues,
Employee Referrals has been our leading source of hire at Synopsys in India. We are actively recruiting throughout India for certain positions described below. We welcome references of talent with good values and technical capabilities; someone whom you have
either worked previously with or know personally or received good feedback. The organization believes in building an inclusive culture and employee referrals are considered to be most important channel of recruitment.
Please refer for following openings in your Professional / Social network such as
LinkedIn, Facebook, Twitter, Former colleagues. Help us get the word out there that Synopsys is a great place to work! . Detailed job description can be looked at (http://teamhr/staffing/erp/Pages/Login.aspx
) by searching against the req number / job id.
Featured Jobs - Synopsys NCR, Bangalore, Hyderabad
|
Job ID & Title: Sr Application Consultant for Synthesis and Timing Location :- Hyderabad Experience in Synthesis / Low Power / Static Timing Analysis (STA) with 5+yrs ** (pls share the resume with Staffing directly) |
Job ID & Title: Multiple reqs, 7614BR, 7615BR, 7616BR & 7617BR, R&D Engineer, Sr.I (for Emulation Team-Transactor Development)
Location: - Noida
|
Job ID & Title: Multiple reqs, 7836BR, 7865BR, 7866BR (R&D Engineer, Sr I, Sr II and Staff-Grade 66 to 68) Location:- Bangalore Keywords:- C/C++, Unix, DS, Algorithm, EDA tool development (Low power/ Static/Formal verification/ FPGA logic synthesis) |
|
|
Job ID & Title: 7017BR, CAE Sr I Location :- Hyderabad Keywords: PDK and overall design flow, knowledge of scripting languages like Python, Tcl or other EDA extension languages |
Job ID & Title: 7751BR & 7752BR, R&D Engineer Sr. I
(Architecture IP Development) Location: - Noida
|
Job ID & Title: 7215BR, Apps Consultant, Staff Keywords:- ASIC design experience in all aspects of physical design, place & route domain (direct IC Compiler, Magma, SOC Encounter, AtopTech ).Knowledge of each step in the process of RTl to GDS II design flow. Location: Bangalore |
|
|
Job ID & Title: 6933 BR , Sr R&D Engineer. Location :- Hyderabad Design engineer with 5+yrs experience in RTL, Synthesis, Timing ,DFT and deep understanding of asynchronous clock crossings |
Job ID & Title: 7373BR, R&D Engineer Sr II ( for Verification IP Development) Location: - Delhi/Noida Keywords: Highly proficient in System Verilog, Methodology knowledge- worked on any verification methodology (OVM,UVM,VMM), Protocol Knowledge - worked on atleast one protocol (AMBA AHB & AXI / USB / PCIe/Ethernet/SATA/OCP/MIPI/HDMI/I2C/SIO /eMMC-5.0/SD-4.0 |
Job ID & Title: 7181066 ASIC/Layout Design Engr, Sr I. Location: Bangalore. Keywords:- Standard Cell layout, Good understanding of CMOS layouts and process technology in 28nm and smaller, ASIC physical design flow: LEF generation, Place & Route, standard cell abutment rules and requirements, EM and IR considerations, DFM, etc. |
|
|
Job ID & Title: 5118 / 5119 BR, ASIC/Layout Design Engr, Sr II Location :- Hyderabad Keywords : Memory full custom layout design , Physical Design methodologies / Phases , CMOS , Fabrication Methodology |
Job ID & Title: 7780BR & 7781BR, (R&D Engineer Sr I) Keywords: Strong hands-on experience in C/C++ based software development, Strong background in OOP, data structure, algorithms, and programming concepts, Exposure to debugging tools such as gdb, Visual Studio, Experience in EDA domain, Scripting (TCL, Python, Shell, perl, etc), Experience with Qt based development, Exposure to Linux and Windows platforms |
Job ID & Title: 7726BR, Design Consultant, Sr I Keywords:- Experience doing Physical Design of complex blocks and/or FullChip designs. |
|
|
Job ID & Title: 5697 / 5698 BR, R&D Engineer, Sr Location :- Hyderabad Keywords: SRAM, ROM, Memory compiler, memory circuit design, CMOS, DRC, LVS, Parasitic extraction, Bit Cell Analysis, Architecture, Characterization, FINFET |
Job ID & Title: 6939BR & 7413BR, R&D Engineer Sr. I, R&D Engineer II (SystemC Modeling for Architecture IP Development team ) Location: - Noida
|
Job ID & Title: 7647BR, Regional Sales Manager -Drive revenue within key accounts Identify, prospect, and qualify new opportunities to grow revenue. |
|
|
Job ID & Title: 7695/ 7694 / 7792 IT Support Admin:- Hyderabad 3 yrs of s/w & h/w troubleshooting exp including 2 years of customer service /phone support for IT. Exp / knowledge of LAN/WAN, including TCP/IP and DHCP are preferred. |
Job ID & Title: 6627BR & 6142BR (Manager R&D -Memory Circuit Design) Location: - Noida
|
Job ID & Title: 7348BR & 7010BR (Memory Circuit Design Engineer Sr. I & Memory Circuit Design Engineer II).
Location: - Noida
|
|
|
Job ID & Title: 7746/7747 / 7749 BR, Analog Layout Engineer Location :- Hyderabad Keywords:-Analog and mixed signal Layout, CMOS circuits, high speed logic paths, layout techniques (ESD, Latchups). Managing and growing team exp |
Job ID & Title: 7698BR (System Admin II - Windows System Administrator with expertise in Scripting) Location: - Noida
|
Job ID & Title: 7731 BR, R&D Engineer, I Location :- Hyderabad Keywords:-C, C++, Perforce, Porting, good knowledge of compilers & data structures along with Shell / Perl scripting experience. |
Arulananda Arul
is the location fixed. my resume matches only for Hyderabad ...
can you check on this.
On 1/6/15, Theiventhiran Murugan <ursev...@gmail.com> wrote:
> Hi Mahesh and other friends,
> There are new openings in Synopsys (Bangalore, Hyderabad and Noida
> location). Please go through the below openings and let me know if it
> matches with your profile.
>
> Regards,
> M. Theiventhiran
> Something is Better than Nothing
> +919986962627
>
> ---------- Forwarded message ----------
> From: Theiventhiran Murugan <Theiventhi...@synopsys.com>
> Date: Tue, Jan 6, 2015 at 6:10 PM
> Subject: FW: Please read: Critical Requirements. Employee Referrals/
> Internal Applications Invited
> To: "ursev...@gmail.com" <ursev...@gmail.com>
>
>
>
>
>
>
> *Sent:* Tuesday, January 06, 2015 5:41 PM
> *To:* all-in01-employees; all-in02-employees; all-in25-employees;
> all-in65-employees; all-in75-employees
> *Subject:* [all-in01-employees] Please read: Critical Requirements.
>
>
>
> Synopsys Employee Referral Program
> Make a difference!
>
> Dear Colleagues,
>
> Employee Referrals has been our leading source of hire at Synopsys in
> India. We are actively recruiting throughout India for certain positions
> described below. We welcome references of talent with good values and
> technical capabilities; someone whom you have either worked previously with
> or know personally or received good feedback. The organization believes in
> building an inclusive culture and employee referrals are considered to be
> most important channel of recruitment.
> Please refer for following openings in your Professional / Social network
> description can be looked at (http://teamhr/staffing/erp/Pages/Login.aspx )
> by searching against the req number / job id.
>
>
>
> *Job ID & Title: Sr Application Consultant for Synthesis and Timing*
>
> Location :- *Hyderabad*
> Experience in Synthesis / Low Power / Static Timing Analysis (STA) with
> 5+yrs ** (pls share the resume with Staffing directly)
>
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>
> bus functional models & verification IP, RTL modeling preferably with FPGA
> based design/synthesis flows, Methodologies using OVM/ UVM, Exp. in of
> design /verification with electronic interface standards: PCIe, USB,
> MIPI,AMBA, HDMI/MHL etc, Developing VIP based on Accelera SCEMI2.x
> standard, Verification of designs on RTL/gate level logic emulators, C/C++,
> OOP.
>
> Sr II and Staff-Grade 66 to 68)*
> Location:- Bangalore
>
> Keywords:- C/C++, Unix, DS, Algorithm, EDA tool development (Low power/
> Static/Formal verification/ FPGA logic synthesis)
>
>
>
>
> Location :- *Hyderabad*
> Keywords: PDK and overall design flow, knowledge of scripting languages
> like Python, Tcl or other EDA extension languages
>
> Development)
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=927382&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=927382_5359&phid=8629>Location:
> - Noida
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>*
> Memory Controller, Memory Protocols DDR3/DDR4/LPDDR, DDR Cycle Accurate
> Memory Models, Embedded Software Design (ESW), SystemC, TLM
>
> Keywords:- ASIC design experience in all aspects of physical design, place
> & route domain (direct IC Compiler, Magma, SOC Encounter, AtopTech
> ).Knowledge of each step in the process of RTl to GDS II design flow.
> Bangalore*
>
> *Job ID & Title: 6933 BR , Sr R&D Engineer. *Location :-* Hyderabad*
> Design engineer with 5+yrs experience in RTL, Synthesis, Timing ,DFT and
> deep understanding of asynchronous clock crossings
>
> Development) Location: - Delhi/Noida
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>*
> Keywords: Highly proficient in System Verilog, Methodology knowledge-
> worked on any verification methodology (OVM,UVM,VMM), Protocol Knowledge -
> worked on atleast one protocol (AMBA AHB & AXI / USB /
> PCIe/Ethernet/SATA/OCP/MIPI/HDMI/I2C/SIO /eMMC-5.0/SD-4.0
>
> Bangalore.*
> Keywords:- Standard Cell layout, Good understanding of CMOS layouts and
> process technology in 28nm and smaller, ASIC physical design flow: LEF
> generation, Place & Route, standard cell abutment rules and requirements,
> EM and IR considerations, DFM, etc.
>
>
> Location :- *Hyderabad*
> Keywords : Memory full custom layout design , Physical Design methodologies
> / Phases , CMOS , Fabrication Methodology
>
>
> *Location: - Noida
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>*
> Keywords: Strong hands-on experience in C/C++ based software development,
> Strong background in OOP, data structure, algorithms, and programming
> concepts, Exposure to debugging tools such as gdb, Visual Studio,
> Experience in EDA domain, Scripting (TCL, Python, Shell, perl, etc),
> Experience with Qt based development, Exposure to Linux and Windows
> platforms
>
> Keywords:- Experience doing Physical Design of complex blocks and/or
> FullChip designs.
> - Should have good understanding of timing, power and area trade-offs. -
> Able to pickup new flows, learn on the job & influence QOR is a must. -
> Exp. delivering designs with multiple voltage islands is a plus.
>
> *Job ID & Title: 5697 / 5698 BR, R&D Engineer, Sr *
>
> Location :- *Hyderabad*
> Keywords: SRAM, ROM, Memory compiler, memory circuit design, CMOS, DRC,
> LVS, Parasitic extraction, Bit Cell Analysis, Architecture,
> Characterization, FINFET
>
> II (**SystemC
> Modeling for Architecture IP Development team **) *
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=927382&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=927382_5359&phid=8629>
>
> *Location: - Noida**
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>*
> of SystemC & TLM, Embedded Software, Understanding of Processors from
> ARM/Tensilica / IBM/Peripheral model internals/ Interconnects like AXI/ AHB
>
>
> -Drive revenue within key accounts Identify, prospect, and qualify new
> opportunities to grow revenue.
> - Manage complex sales cycle, including mapping out of sophisticated
> experience.*
> technical solution
>
> 3 yrs of s/w & h/w troubleshooting exp including 2 years of customer
> service /phone support for IT. Exp / knowledge of LAN/WAN, including TCP/IP
> and DHCP are preferred.
>
>
> *Location: - Noida
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>*
> LVS, Parasitic extraction, Bit Cell Analysis, Architecture Design,
> Characterization, FINFET
>
> Parasitic extraction, Bit Cell Analysis, Architecture Design,
> Characterization, FINFET
>
>
> Location :- *Hyderabad*
> Keywords:-Analog and mixed signal Layout, CMOS circuits, high speed logic
> paths, layout techniques (ESD, Latchups). Managing and growing team exp
>
> with expertise in Scripting)*
>
> *Location: - Noida
> <https://sjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?jobId=951032&PartnerId=25235&SiteId=5359&JobReqLang=1&JobSiteId=5359&JobSiteInfo=951032_5359&phid=8241>*
> Experience in Windows Administration of Server 2003, 2008, 2008 R2,
> Win 2012 OS, Windows 7, installation, troubleshooting, patch management,
> Understanding of Windows Infrastructure technologies (e.g. AD, GPO, CIFS,
> NFS, DFS), Knowledge on Citrix Administration and VMWare
>
>
> Location :- *Hyderabad*
> Keywords:-C, C++, Perforce, Porting, good knowledge of compilers & data
> structures along with Shell / Perl scripting experience.
>
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>
Theiventhiran Murugan
Arulananda Arul
keep us updated on job offers.
thank you
arul
On 1/7/15, Theiventhiran Murugan <ursev...@gmail.com> wrote:
> Hi Arul,
> As i understand from my group (Solutions Group), there are no current
> openings in Bangalore location (atleast near future). So getting internal
> transfer from one location to another may not be so easy at this time. So
> to answer to your question is, the location is fixed for these openings...
>
> Regards
Mahesh Penugonda
Arulananda Arul
How many years exp you have. there is opening at Cannon for 8+ years.
will you be interested ?????
On 1/12/15, Mahesh Penugonda <mahesh.p...@gmail.com> wrote:
> Hi Theiven,ouears havars of exp y
Mahesh Penugonda
Arulananda Arul
Mahesh Penugonda
Kishan
From: Arulananda Arul
Sent: 12-01-2015 16:49
To: arasan_...@googlegroups.com
Subject: Re: FW: Please read: Critical Requirements. Employee Referrals/Internal Applications Invited