Query regarding time datatype.
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haripriya patil
Aug 10, 2012, 5:21:21 AM8/10/12
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Hi All,
Why time has been defined as 4 State variable in systemverilog LRM even though it cannot take 'X' or 'Z'?
Any idea friends??
Best Regards,
Haripriya
Why time has been defined as 4 State variable in systemverilog LRM even though it cannot take 'X' or 'Z'?
Any idea friends??
Best Regards,
Haripriya
arulananda arul
Aug 23, 2012, 2:48:18 AM8/23/12
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Hi haripriya.
Time is verilog 2001 LRM data type and not sv data type. hence it is four state.
Hope that answers you question ....
haripriya patil
Aug 23, 2012, 4:36:10 AM8/23/12
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yah that is true . But why they cannot change it now to 2-state as that is avaliable now.
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