US-TX, ASIC Design Engineer/Verilog, CV Associates

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JOB TITLE: ASIC Design Engineer/Verilog
LOCATION: Austin, US-TX
JOB TYPE: Direct
SALARY : $85000 - $100000

DESCRIPTION:
This positions requires ASIC design experience with a solid understanding of
the VLSI circuit design process, including the use of Verilog HDL and a
synthesis-based design methodology. Applicants should have experience with
Synopsys Design Compiler, Verilog simulation tools and static timing analysis.
Experience in FPGA implementation is desired. A prior working knowledge of PC
architecture and ISA/USB/PCI/PCMCIA bus protocols would also be helpful, as
these are the typical interfaces that our chips use to transfer data to/from
the network and the PC.

MANDATORY SKILLS:
ASICs;Electrical Engineer;Chips;CIRCDSGN (Circuit Design);Designer;Field
Programmable Gate Array;PCMCIA;Protocols;Simulate;Static Analysis;Synopsys (or
Synopsis);Synthetics;Verilog HW Modeling;Very Large Scale ICs;PCI BUS
(Periph.Compon.Interc

MANDATORY EDUCATION: Bachelor of Science

Please refer to Job#: 00968772-TE in all correspondence about this job.

CV ASSOCIATES
Vince Quiros
Apply for this Job, please click on the link below.
http://www.topechelon.com/applyjob.asp?JobID=00968772

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