CA, San Jose / ASIC Design Engineer (RECRUITER)

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POSITION ID: kb.194
DATE POSTED: 3/17/99
DURATION : Direct Hire

POSITION TITLE: ASIC Design Engineer
INDUSTRY: Computer Hardware; Telecom/Wireless; Telecommunications

FUNCTION: HARDWARE ENGINEERING

LOCATION: California - San Jose
KEYWORDS: High-Speed ASIC Design, Complex Network ASICs, Verilog, Synopsys, Static Timing, Perl, Unix

COMPENSATION: Open

COMMENTS:
You will define micro-architectures and implement logic for a high
performance network switch ASIC. This position includes significant
equity participation.

INSTRUCTIONS:
REQUIREMENTS:
-- Proven track-record of design of complex, high-performance
network ASICs.
-- 4+ years of relevant experience with high-speed ASIC design.
-- Experience with Verilog, Synopsys, static timing, Perl, Unix.
-- BSEE or equivalent required.

DUTIES/RESPONSIBILITIES:
You will help define a major portion of a standard cell ASIC and be
responsible for driving the design through HDL coding, verification,
synthesis, static timing analysis, to tape-out.

CONTACT:

TransWeb, Inc.
Lori Kalnins
43680 Tonica Road
Fremont, CA 94539
Tel: 510-683-9321
Fax: Call for Fax #

E-MAIL ID: 510-68...@smart-office.net
URL: http://www.smart-office.net/510-683-9321.html

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