CA, San Jose / Senior ASIC Design Engineer (RECRUITER)

[Recruiters OnLine Network -RON]

Please reply to recruiter listed below. Do not reply to quic...@jobs-net.net

------------------------------------------------------------------------------
POSITION ID: kb.193
DATE POSTED: 3/17/99
DURATION : Direct Hire

POSITION TITLE: Senior ASIC Design Engineer
INDUSTRY: Computer Hardware; Telecom/Wireless; Telecommunications

FUNCTION: HARDWARE ENGINEERING

LOCATION: California - San Jose
KEYWORDS: High-Speed ASIC Design, Complex Network ASICs, Verilog, Synopsys, Static Timing, Perl, Unix

COMPENSATION: Open

COMMENTS:
This position includes significant equity participation.

INSTRUCTIONS:
REQUIREMENTS:
-- Proven track record of design of complex, high-performance
network ASICs.
-- 7+ years of relevant experience with high-speed ASIC design.
-- Extensive experience with Verilog, Synopsys, static timing,
Perl, Unix.
-- BSEE or equivalent required.

DUTIES/RESPONSIBILITIES:
You will be developing standard cell based ASICs which implement the
core architecture of the client’s network switching technology. You
will help define overall chip architecture and partitioning, and then
drive design and debug of a major portion of the ASIC through to tape-
out and prototype bring-up.

CONTACT:

TransWeb, Inc.
Lori Kalnins
43680 Tonica Road
Fremont, CA 94539
Tel: 510-683-9321
Fax: Call for Fax #

E-MAIL ID: 510-68...@smart-office.net
URL: http://www.smart-office.net/510-683-9321.html

------------------------------------------------------------------------------

This message was distributed by the Recruiters Online Network.

To use our QuickSearch to search 1000's of job openings or to post your
resume at no charge visit our world wide web site at
Main Page: http://www.ipa.com/
Job Search: http://www.ipa.com/search.html
Find Recruiters: http://www.ipa.com/members
Free Resume Post: http://www.ipa.com/careers/resumemail.html