ABM Risc Processor Core

[antti....@googlemail.com]

Hi

maybe i need to work on the name (Advanced Brain Machine), but the
concept seems to be finalized for a small, optimized soft processor
core that is high level compiler and multi threading friendly.

some pre-release infos:
---------------------------------
* 8 bit Alu/Datapath
* Windowed Register File, 16 Registers in each context
* optimized to work from single block RAM
- minumum 1 BRAM with 256x16 + 512*8 aspect ratios needed (address can
be larger)
* Not using distributed RAM (friendly for Altera, Actel, Silicon
Blue..)
* Fast context switch
- nested interrupts and/or
- thread switching
* Instruction cycle 4 clocks
* All Instructions execute in one cycle

yes, there is a compromise, it is not executing 1 CPI (clock per
instruction), but wasting 4 clocks.
I tried to use only 2 clocks per instruction but it really isnt
possible.

sure it possible to have soft core processors to run 1 clock per
instruction, but for the goal it
really isnt possible, there are delays for fetching code and
registers, and if all has to be streamed
from/to single BRAM there is a need for more then 1 clock per
instruction.

more details to follow.. :)

Antti