Some hints for SiBlue iCE65 FPGA designs

[Antti....@googlemail.com]

some hints for iCE65 designs, mostly for PCB technology constrained
designs that do not need all I/O

What needs to be powered (absolute minimum)

VCCINT
VCCIO2
VCC_SPI
VCCIO1 *
VPP_2V5 *

early datasheet does say that VPP_xxx can be grounded if not used,
this is not the case for the production silicon (including V
versions).

VCCINT can be routed out via I/O of the powered I/O banks

It is NOT OK to power bank 3 with 1.2V, if 1.8 or 2.5 is not available
then bank 3 should be left unconnected completly (including its power
supply)

unused IO leave OPEN

OK to use route via unused IO of powered banks, but consideration with
the pullups if different IO bank voltages are used (possible reverse
current).

configuration pins: CDONE,CRESET,CBSELx can leave open but routing out
CRESET will help programming the SPI flash on board as otherwise the
FPGA would try to configure and may hinder the SPI flash programming.
CRESET pin is inner ball, so some trick can be done to avoid the need
to route it out. Drive SS low at power up, and configure the FPGA via
external programmer (need to make sure the onboard SPI flash does not
conflict!). Use VPP_2V5 to delay configuration (it is outer row,
easier to access).

The above are hints and tips as I am aware as of today, it is
recommended to contact SBT if any questions about the correct wiring
arise.

Antti