JTAG indirect SPI programming IP core

[antti....@googlemail.com]

found from old project:

JTAG-SSI-SPI bridge IP
it has been used internally to flash SPI devices connected to various
FPGA's
the ip core connect directly to xilinx BSCAN

included is example SVF file that when played onto the device will
verify some
ST spi flash device ID



***********************************

--------------------------------------------------------------------------------
-- Company: Trioflex OY.
-- Engineer: Antti Lukats
--
-- Create Date: 10:07:52 12/02/05
-- Design Name:
-- Module Name: ssi_to_spi - Behavioral
-- Project Name: JTAG-SPI Bridge
-- Target Device: Any FPGA with Fabric accessible JTAG primitive
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- 0.02 - added comments
-- Additional Comments:
--
--// Simple Serial File format input
--// Verify ID code of ST M25P32 SPI Flash:
-- SPI SDI 9FFFFFFF SDO 00202016 OMASK 00FFFFFF IMASK FF000000;
--// Generated SVF:
-- SDR 44 TDI (FFFDFEFF7CB) TDO (FB44120900F) MASK (07FBFDFE000) SMASK
(FC020100FFF);
--
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ssi_to_spi is Port (
SSI_CLK : in std_logic; -- Clock BSCAN: connect to DRCKx
SSI_DI : in std_logic; -- Data In BSCAN: connect to TDI
SSI_DO : out std_logic; -- Data Out: connect to TDOn
----------------------
SSI_CE : in std_logic; -- Clock Enable BSCAN: connect to SHIFT
SSI_RST : in std_logic; -- Reset BSCAN: connect to RESET
SSI_EN : in std_logic; -- Enable BSCAN: connect to SELn
----------------------
SPI_CS : out std_logic; -- active HIGH select, use inverse to SPI
Flash chips
SPI_SCK : out std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic
);
end ssi_to_spi;

architecture Behavioral of ssi_to_spi is

signal Count8 : std_logic;
signal Count8d : std_logic;
signal Count8d_0 : std_logic;

signal CS_i : std_logic;
signal BitCount : std_logic_vector(3 downto 0);

begin
SPI_CS <= CS_i;


Process_Latch : process (SSI_CLK, CS_i, Count8) is
begin
if SSI_CLK = '0' then
SPI_SCK <= '0';
else
if (SSI_CLK='1' and CS_i='1' and Count8d_0='0') then
SPI_SCK <= '1';
end if;
end if;

end process Process_Latch;


-- SPI_SCK <= SSI_CLK and CS_i and not Count8d;

SPI_DO <= SSI_DI;
Count8 <= '1' when BitCount="1000" else '0';

Process_SSI_CLKF : process (SSI_CLK) is
begin
if SSI_CLK'event and SSI_CLK = '0' then
Count8d_0 <= Count8;
end if;
end process Process_SSI_CLKF;


Process_SSI_CLK : process (SSI_CLK) is
begin
if (SSI_RST='1') then
CS_i <= '0'; -- Clear Chip Select
BitCount <= "1000";
SSI_DO <= '1';
else
if SSI_CLK'event and SSI_CLK = '1' then
-- SPI Data is available from falling
-- edge so lets latch it on rising edge
-- Out is High if not active, with 1 clock low start pulse
SSI_DO <= (SPI_DI or not CS_i) and not (Count8 and not CS_i and not
SSI_DI);
--
if (SSI_CE='1') then
Count8d <= Count8;
if (Count8='1') then
CS_i <= not SSI_DI;
end if;
if (BitCount="0000") then
BitCount <= "1000";
else
if ((CS_i='1') and (Count8='0')) or ((Count8='1') and
(SSI_DI='0')) then
BitCount <= BitCount-"0001";
end if;
end if;

end if;
end if;
end if;
end process Process_SSI_CLK;

end Behavioral;