Multi Stage Amplifier Design

[Pernille Pennebaker]

Formy final lab this semester, I've been tasked with designing a multi-stage amplifier that serves as a receiver in a laser tag set that we've been building over the course of the class. I've searched various forums, but have only found loose advice on how to go about designing the amplifier.

So, as you can see, I have a 4 stage amplifier in the pattern of CE, CC, CE, CC. The way I see it, I have at least three major design steps to this project. First, I must determine the resistor values 1 through 14 such that my gain is the adequate amount. Second, I must determine the capacitor values to make the amplifier also function as a bandpass filter. Lastly, I need to limit my output to 1 V.

I'm fairly inexperienced with the design process. I know I'll need to calculate the gain, input resistance, and output resistance for each individual stage, but after that, I'm uncertain of which values to start tinkering with or adjusting to attain my goals. Before anyone jumps down my throat for wanting people to do my work for me, let me make my goal clear: I am looking for design techniques and a process that will help me solve this problem--hints in the right direction. I would be disappointed with this great community if anyone simply solved it for me. Would someone be willing to point me in the right direction?

Design is fun because you have so many choices. Here are some rules of thumb to help you with the Q1 stage. Your have three main concerns; bias stabiltiy, gain, and frequency response. Start by biasing Q1. You get to pick your bias current. Let's choose 0.1mA because the transistor still has decent beta and it leaves you 0.9mA to play with. Next pick the collector voltage. Let's use 6v. Now we know R2=30k. For now, just assume Ic=Ie. it is close enough for what we are doing here. Next pick the emitter voltage to be 2V. Why? Because we can. This means R8 is 20k. A rule of thumb here is to choose R7 to be 10 time R8. So make it 200k. Now we do a calculation to calculate R1. Since emitter is 2V the base voltage as 2.7V. R7 current is about 13.5uA. The base current is about 0.0001/30=3.3uA. Then R1 will 9V-2.7v over the sum of these currents about 38k. So we have a basic stable stage with low gain, aprox 30k/20k or 1.5. The is because R8 is providing local feedback. This is good for DC stability but bad for gain. The solution for this is to put a capacitor across R8. Now we still have good stability because of the DC feedback but a lot of gain because we have reduced the AC feedback. Pick this capacitor to give you the low frequency corner you are looking for. You may have to split R8 into two resistors and only bypass part of the emitter resistor to get good balance of characteristics. If you have access to a simulator, you might try this. Your final bias will not be exactly 2.7 at the base or 6 at the collector but should be in the ball park. From this starting point you can make modifications and hopefully get what you need. Other stages can be designed similarly but will interact. Your emitter follower after the first stage will help prevent this but cost you current for no voltage gain. Have fun.

For most systems a single transistor amplifier does not provide sufficient gain or bandwidth or will not have the correct input or output impedance matching. The solution is to combine multiple stages of amplification. We have the three basic one transistor amplifier configurations to use as building blocks to create more complex amplifier systems which can provide better optimized specifications and performance. The sections in this chapter tend to use BJT devices to illustrate the circuit concepts but these multi-stage amplifiers can be constructed from MOS FET devices, or a combination, just as easily and the methods used to analyze them are much the same as well.

As we would expect, the overall equation reduces to the ideal case of AV = A1*A2 for two ideal stages when we let the Rout go to 0 and the Rin go to infinity. As a matter of fact, we really only need Rout to go to 0 to have the resistor dividers to go to 1. The above equations assume that the individual amplifier gains, A do not change with output loading. That effect, if any, is modeled in the Rout.

For most integrated circuit amplifiers where Rin is in the MΩ to GΩ range, and Rout is in the 50 to 100 Ω range, the gains are pretty close to being the simple product of the gain stages. To confirm this assertion, assume a low performance op amp with Rout = 100Ω and Rin = 1MΩ, what is the gain with two stages of gain A1 and A2 in series? (assume RL = 1 MΩ)

The answer is pretty close to A1*A2. In fact, you would have to go to a cascade of 100 stages with these specifications before you even lost 1% of the expected ideal gain (i.e. to get 0.99 A100). By the time you reached that point, other adverse effects would have caused much more trouble, for example, the fact that noise from each successive stage is added to the noise coming into that stage and is further amplified on down the cascade of amplifiers.

The impact of input and output loading can be minimized by cascading two amplifiers with appropriate input and output characteristics. Multistage cascading can be used to create amplifiers with high input resistance, low output resistance and large gains.

The cascade of a Common Emitter amplifier stage followed by a Common Collector (emitter-follower) amplifier stage can provide a good overall voltage amplifier, figure 10.1.1. The Common Emitter input resistance is relatively high and Common Collector output resistance is relatively low. The voltage follower second stage, Q2, contributes no increase in voltage gain but provides a near voltage-source (low resistance) output so that the gain is nearly independent of load resistance. The high input resistance of the Common Emitter stage, Q1, makes the input voltage nearly independent of input-source resistance. Multiple Common Emitter stages can be cascaded with emitter follower stages inserted between them to reduce the attenuation due to inter-stage loading.

Calculating the DC biasing conditions and the required resistance values for each stage in the cascade is preformed just as we have done in the previous chapter on single stage amplifiers. The effect of inter-stage loading must then be take into account as we just discussed in the opening section of this chapter.

The complication in calculating the gain of cascaded stages comes from the non-ideal coupling between stages due to loading. Two cascaded common emitter stages are shown in figure 10.1.2. Because the input resistance of the second stage (resistors R3 and R4) forms a voltage divider with the output resistance (RC1) of the first stage, the total gain is not simply the product of the gain for the individual (separated) stages.

The total voltage gain can be calculated in either of two ways. First way: the gain of the first stage is calculated including the loading of the R3,R4 resistor divider. Then the second-stage gain is calculated from the collector of Q1 which is the output of the first stage. Because the loading (R3,R4 output divider) was accounted for in the first-stage gain, the second-stage gain input quantity is the Q2 base voltage, vB2 = vo1.

Second way: the first-stage gain is found by disconnecting the input of the second stage, thereby eliminating output loading. Then the Thevenin equivalent output of the first stage is connected to the input of the second stage and its gain is calculated, including the input divider formed by the first-stage output resistance and second-stage input resistance. In this case, the first-stage gain output quantity is the Thevenin equivalent voltage, not the actual collector voltage of the amplifier with the second stage connected. The second way includes inter-stage loading as an input divider in the gain of the second stage while the first way includes it as an output divider in the gain of the first stage.

It is possible to create a multistage cascade where each stage is separately biased and coupled to adjacent stages via DC blocking capacitors. Inserting coupling capacitors between stages blocks the DC operating bias level of one stage from affecting the DC operating point of the next. This solves many of the limitations we saw in section 10.1.2. However, the resulting overall amplifier can no longer respond to DC, or very low frequency, inputs.

The infinity symbol next to coupling capacitors C1 C2 and C3 is used to indicate that the unspecified capacitance is large enough at the specified signal frequency to have a negligible reactance and can be treated as an AC short-circuit. It is also useful to note at this point that the method of including capacitors across the emitter degeneration resistors RE1 and RE2 to increase the gain at higher frequencies can be employed in the case of these multistage amplifiers as well as the single stage amplifiers discussed in Chapter 9.

Not only can NPN transistors or n-type MOS devices be combined in multiple stages, so can the complementary PNP and p-type MOS devices. Having both polarities of transistors allows for more flexibility in how amplifier sages can be combined and can make biasing easier as well.

A two-stage 'Complementary Pair' BJT amplifier circuit diagram is shown in figure 10.1.4. The rationale behind a complementary pair cascade is a problem that can arise with a cascade of similar n-type stages. To avoid saturation the collector voltage of each stage must be greater than the base voltage, enough greater to allow for the collector voltage signal swing. However since the base voltage of the second stage is taken from the collector of the first stage it is inherently larger that the first stage base voltage, and the second stage collector voltage is still higher. But this decreases the available amplitude for the amplified signal. Adding a third stage would even further aggravate this situation.

If a PNP second stage is used a base voltage close to the positive power supply accommodates a desirable higher first stage NPN collector voltage. Moreover a third NPN stage can be cascaded at the PNP stage output without the severe voltage offset problem of a cascade of similar stages.

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