TD8E compatibility?

[Bob Armstrong]

I know that the TD8E would not work with certain memory and/or CPU combinations because speed problems. The TD8E uses programmed I/O to transfer each line of DECtape data and the timing just barely works. But I don't know/can't remember the exact rules. Can anybody remind me?

I believe that the KK8E CPU with MM8E core memory WORKS.

I believe the KK8E CPU with the MM8A core memory WORKS (i.e. an 8/E CPU in a BA8C chassis).

I think the KK8A CPU with MM8A memory also works (i.e. 8/A CPU in an 8/A chassis).

I think that either CPU with the MS8C (8/A MOS memory) DOES NOT work (presumably because of the refresh delays).

Am I right? Are there any more combinations that are OK or not OK? Is the MS8C the only combination that doesn't work? Were there any other memory options that I've forgotten?

Thanks!

[Bob Armstrong]

Could anyone at least confirm or deny whether an MS8C or MS8D (M8417 or M8418) will work with the TD8E? I have this combination and I'd like to know if I'm chasing a hardware problem, or if it's just something that never worked.

[Steve Tockey]

Bob,
Unfortunately I’m not in any position to confirm anything. Sorry. That said, the issue with TD8E/TU56 on PDP-8s is apparently ultimately timing. Because the CPU is intimately involved in TU56 data transfer and even an -8/e/m/f was right at the ragged edge with a 1.2 uSec cycle time. I seem to remember that either the -8/a had a 1.5 uSec cycle time like earlier -8s, or at least certain configurations of the -8/a had 1.5 uSec cycle times, then it seems reasonable that your fear is well founded. Can you check—either through documentation or by empirically measuring (e.g., oscilloscope)—the cycle time? If it is running at 1.5 uSec then that could easily be the explanation.

To be precise, if you are running a 1.2 uSec cycle time then it is NOT the problem because -8/e/m/f run TU56 successfully at that speed. OTOH if you are running 1.5 uSEc or greater then that COULD be the root cause.


I hope this helps...

[Bob Armstrong]

On Wednesday, June 3, 2020 at 4:50:33 PM UTC-7, Steve Tockey wrote:
> To be precise, if you are running a 1.2 uSec cycle time ...

Sorry, I should clarify that my PDP-8/A has a KK8E CPU. An 8/E CPU in an 8/A chassis was an official DEC configuration, the 8A600 and 8A800 family. So, unless memory interferes, it's the same speed as an 8/E.

The real question is whether the MS8C or D can ever delay the CPU for a memory refresh. From the manual it appears that the C or D versions have a transparent refresh cycle that fits into time when the memory would otherwise be idle, so the CPU is never forced to wait.

At least that's the theory. I haven't really found a definitive statement about this, or about TD8E compatibility in general. I know that the timing is very tight for this peripheral, and there's not much margin for delays.