FPGA PDP8e

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David Armstrong

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Mar 31, 2022, 9:04:51 PMMar 31
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There was a question asked in a previous conversation about how much memory did my FPGA PDP8e have? The answer is 8k (x12)

A little more information, some pictures and the FPGA resource utilization are at :

https://pdp8e.blogspot.com/

Regards Dave

Rich Alderson

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Apr 1, 2022, 8:09:56 PMApr 1
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Just curious: Since you went beyond the single field 4KW memory anyway, why
not go all the way to 32KW?

--
Rich Alderson ne...@alderson.users.panix.com
Audendum est, et veritas investiganda; quam etiamsi non assequamur,
omnino tamen proprius, quam nunc sumus, ad eam perveniemus.
--Galen

Scott Lurndal

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Apr 2, 2022, 10:50:08 AMApr 2
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Rich Alderson <ne...@alderson.users.panix.com> writes:
>David Armstrong <davidarm...@gmail.com> writes:
>
>> There was a question asked in a previous conversation about how much memory
>> did my FPGA PDP8e have? The answer is 8k (x12)
>
>> A little more information, some pictures and the FPGA resource utilization
>> are at :
>
>> https://pdp8e.blogspot.com/
>
>Just curious: Since you went beyond the single field 4KW memory anyway, why
>not go all the way to 32KW?

I believe that David noted that he was using pretty much
all the available RAM on the FPGA he was using.

David Armstrong

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Apr 2, 2022, 3:32:38 PMApr 2
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Yes, that is correct, I use 24 of the 32 RAM blocks on the FPGA. There is another member of this FPGA family, the ICE40up5K, which would have enough RAM for the full 32K or even the 128K of the PDP8a, but it does not have enough dedicated IO to deal with the LEDs and switches without extra circuitry. I really did not want to give up the blinken lights.

Rich Alderson

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Apr 2, 2022, 9:13:43 PMApr 2
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David Armstrong <davidarm...@gmail.com> writes:

> On Saturday, April 2, 2022 at 8:50:08 AM UTC-6, Scott Lurndal wrote:
> > Rich Alderson <ne...@alderson.users.panix.com> writes:=20

>>> Just curious: Since you went beyond the single field 4KW memory anyway, why
>>> not go all the way to 32KW?

>> I believe that David noted that he was using pretty much=20
>> all the available RAM on the FPGA he was using.

> Yes, that is correct, I use 24 of the 32 RAM blocks on the FPGA. There is
> another member of this FPGA family, the ICE40up5K, which would have enough
> RAM for the full 32K or even the 128K of the PDP8a, but it does not have
> enough dedicated IO to deal with the LEDs and switches without extra
> circuitry. I really did not want to give up the blinken lights.

OK, curiosity satisfied. Thank you.

Tom Hunter

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Apr 3, 2022, 8:07:15 AMApr 3
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Hi Dave,
I am curious about your PDP-8/e FPGA implementation:

1) is it open source?
2) are you using VHDL or Verilog?

Thanks
Tom Hunter

Rob Doyle

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Apr 3, 2022, 3:24:23 PMApr 3
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I suspect there are many PDP-8 FPGA implementations. I created an open
source PDP8 in VHDL and archived it at:

https://opencores.org/projects/pdp8

Rob Doyle.

Tom Hunter

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Apr 4, 2022, 4:49:07 AMApr 4
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On Monday, April 4, 2022 at 3:24:23 AM UTC+8, Rob Doyle wrote:
> I suspect there are many PDP-8 FPGA implementations. I created an open
> source PDP8 in VHDL and archived it at:
>
> https://opencores.org/projects/pdp8
>
> Rob Doyle.

Hi Rob,

Thank you for the link.

I had a very quick browse through the CPU implementation and I am very impressed that you not just support one PDP-8 model, but seemingly every PDP-8 type ever made including the HD6100 and HD6120.

I note that you support the DE0-Nano development board. As I have one DE0-Nano sitting on my desk I wonder if that is a good choice to try your implementation with. It is set up to emulate a PDP-8/a.

What is needed to interface to it, specifically what did you use as a front-panel? All I/O is 3.3V (LVTTL) which is new territory for me.

Is there any reason why I couldn't reconfigure the DE0-Nano VHDL code for a PDP-8/e (which is my favourite) or a PDP-8/I? Possibly there are not enough spare I/O pins available?

Thanks again for creating this comprehensive implementation in VHDL.

Best regards
Tom Hunter

David Armstrong

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Apr 4, 2022, 11:28:25 AMApr 4
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Tom,
The PDP8e is written in Verilog. It is not yet open sourced, however that is my intent. As Rob has said there are numerous FPGA implementations available. Before I began writing my own, I looked at a lot of them. The most impressive is Robs! I tried to use it on a Lattice semiconductor machxo2 part using the vendor tools. I was unable to get it to fit, even with stripping some parts out.

I had also looked at all sorts of FPGA dev boards, I did not want to spend a lot of money on a board. I eventually settled on a Icewerks board. For tools I use yosys and icestorm. These are command line tools they are orders of magnitude faster than Lattices tools.

Tom Hunter

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Apr 4, 2022, 12:14:18 PMApr 4
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Hi David,

Thanks for your reply.

With all the different implementations I am curious why you decided to write your own?
Was it just the intellectual challenge or did you chose a different approach to Rob's?

Recently I stumbled across Kyle Owen's PDP-8/i implementation which uses an interesting approach by implementing all the flip-chip boards as small Verilog modules and then simply "wire" these modules into a complete PDP-8/i identical to how the real PDP-8/i backplane was wire-wrapped. The resulting implementation is really identical to the real thing except for timing and memory.

There is also another implementation from Folke Will which interfaces directly to the PiDP-8/i front-panel using the ZynqBerry development board.

Best regards
Tom

David Armstrong

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Apr 4, 2022, 5:09:02 PMApr 4
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Why did I implement my own? Well I had an itch to scratch, I am now retired, but the last decade of work was spent architecting large FPGA projects, mostly Xilinx based, usually with a lot of DSP functionality. I would (along with others) sketch out a block diagram, figure out what DSP functions would be needed, often using Matlab to predict the performance required, that then would translate into multipliers, logic, and memory requirements. From there, we would pick an FPGA... depending on how good the estimate was felt to be, inflating the resource usages appropriately. This was all sorts of fun! I took a lot of training on Xilinx FPGA's. However I never really got down to coding... there was always another task showing up. We used VHDL almost exclusively.

So when I retired I wanted to learn about the lower level process of designing with FPGA's. FPGA providers all supply tools, most of them free for their low end chips. I have tried both Verilog and VHDL in these tools, I am not very impressed at the speed of these tools. I then found the Icestorm, yosys and nextpnr tools, they are much faster and on the computer I am using that is important. Yosys accepts Verilog as an input, so here I am coding in Verilog. ( I think it may now accept VHDL as well...)

Well, my approach is different from Rob's. Rob has provide code for a lot of modules of a PDP8. These are relatively small, well structured, organized like the PDP8 module catalog and self contained. The CPU itself is all in one large file, it is readable and well commented and I think well structured. However, I dislike large source files, if I can I use modules of 200 to 300 lines. I have had occasion where it has not been possible... Anyway, so my implementation breaks the CPU down into parts, there is a state machine that drives the CPU, then there are other modules that take use state information, and iop codes to do what they need to do.... There are currently 10 modules. This lets me design a modules, write a test bench for it and simulate it in isolation. This was especially important as I learned Verilog. I am getting better at writing the implementation and the test benches although I have a long way to go before I am good at it...

I looked up the other two implementations you mentioned. I will have to try Kyle Owen's and see what it does.

Dave





Tom Hunter

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Apr 13, 2022, 2:18:52 AMApr 13
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Sorry for the resend. There appears to be no way to directly reply to an author of a message.
Rob Doyle - is there any more information about using your PDP8 implementation on a DE0-Nano?

It builds and programs fine into the DE0-Nano, but without anything connected to the boards headers it won't do much.

Have you got any schematics or design for a plug-on board for what needs to go onto the DE0-Nano headers to make the PDP-8 functional?

It is a bit confusing because you did bring out all the switches but not the data and address LEDs. Also there is code there to show the data via a 4 digit 7 segment display, but that too does not connect to the headers. The 7 of the 8 LEDs which came out are not used but seemed to be some form of debug LEDs which have been commented out.

Is this still work in progress or am I looking at the wrong Subversion branch?

The website is: https://opencores.org/projects/pdp8

I am looking at the code in Subversion under trunk.

Thanks and best regards
Tom Hunter

Rob Doyle

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Apr 15, 2022, 7:39:55 PMApr 15
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> Sorry for the resend. There appears to be no way to directly reply to
> an author of a message. Rob Doyle - is there any more information
> about using your PDP8 implementation on a DE0-Nano?
>
> It builds and programs fine into the DE0-Nano, but without anything
> connected to the boards headers it won't do much.
>
> Have you got any schematics or design for a plug-on board for what
> needs to go onto the DE0-Nano headers to make the PDP-8 functional?
>
> It is a bit confusing because you did bring out all the switches but
> not the data and address LEDs. Also there is code there to show the
> data via a 4 digit 7 segment display, but that too does not connect
> to the headers. The 7 of the 8 LEDs which came out are not used but
> seemed to be some form of debug LEDs which have been commented out.
>
> Is this still work in progress or am I looking at the wrong
> Subversion branch?
>
> The website is: https://opencores.org/projects/pdp8
>
> I am looking at the code in Subversion under trunk.
>
> Thanks and best regards Tom Hunter
>

[snip]

Short answer - someone contributed the DE0-Nano top-level design. I know
that I built it and that it built without errors - just to make sure it
was complete. I have a DE0-Nano but used it for a PDP2011.

You will need an external 3.3V to RS-232 adapter of some sort and if you
want an SD Card socket if you want to implement an RK05 disk drive. It
has been a long time, but I believe the author used a Digilent SD
Card PMOD and a UART/USB PMOD.

If you look at the directory structure, there is fairly generic PDP8
implementation underneath everything which has standardized interfaces
for all of the external interfaces - RS232, Front Panel, RK05,
configuration, etc.

At the top level, you can configure the PDP8 and implement or 'stub
off' the interfaces as you see fit. So, yes, several of the FPGA boards
have 7 segment LED displays. All the switches and LEDS (address and
data bits) are routed to the 'top level' entity. Depending on what top
level entity you're looking at, they may be 'tied off'.

I have a whole design of a front panel board that was intended to be
compatible with my SBC6120 PDP8 unit. It has all the switches, LEDS, an
SD Card, a socket for DE0-nano, 4x RS232 ports, a FT4232 quad USB/UART,
VT52 terminal with VGA video and PS/2 keyboard interfaces, and a WIFLY
module. It's designed in KICAD and is mostly all done. I just never had
time to finish it. By now, it probably has some obsolete parts - and it
would take a little to clean the design up. The FPGA interfaces to bhe
board would need to be implemented - but this is relatively simple.

I'd share that design if someone had the energy to finish it and let me
order one of the boards.

Rob Doyle
doyle (at) cox (dot) net
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