PDP-8/X architecture review request
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johnw...@gmail.com
Jun 25, 2020, 11:37:45 PM6/25/20
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I cut my teeth on the PDP-8 back in the 1970s, and have had only a casual acquaintance with it since. But I got a copy of an open call from a friend for a "32-bit deterministic integer machine", as simple as possible but no simpler. Naturally I thought of the PDP-8; a word machine can have almost any word size without changing much.
The design I ended up with was rejected for the original use, but my friend encouraged me to carry on with the design, which has now produced something I've dubbed the PDP-8/X architecture. I'd appreciate any comments: post them here, send them to co...@ccil.org, or post PRs at https://github.com/johnwcowan/pdp8x.
The design document in that repo assumes zero familiarity with the PDP-8. For this audience I can summarize it like this:
* Words and addresses are 32 bits, but instructions are only 16 bits. This means that when (a) the last instruction before a label or (b) a JMS instruction is stored as the first of the two 16-bit instructions in the word, the assembler needs to fix things up by inserting a NOP after the instruction.
* MRI instructions are the same except that the indirect bit has been rotated to bit 0, so that opcodes 0x0 to 0x6 are direct and 0x8 to 8xD are indirect. The resulting page address is 11 bits, so pages are 2KW instead of 128 words, and you can have up to 2M pages or 4 GW (16 GB) of memory. Plenty of room!
* I/O instructions keep the 0x8000, 0x800, 0x80, and 0x8 bits clear, so that TLS, for example, is now 0x6034.
* OPR instructions likewise rotate the group 1 / group 2 bit to bit 0, so that group 1 has an opcode of 0x7 and group 2 an opcode of 0xF. The same bit spacing pattern used for I/O is used, so that CLA CLL is 0x7300. However, rather than squeezing group 3 (standard only, no EAE) into group 2, MQA and MQL are in the 0x80 and 0x8 bits of group 1, which means they can be microcoded together for instructions like CLA CMA MQL.
* The BSW instruction is split into two: HSW to swap half-words ("UNIX" becomes "IXUN") and BSW to swap the individual bytes of each half-word ("UNIX" becomes "NUXI").
Enjoy, and advTHANKSance.
John Cowan http://vrici.lojban.org/~cowan co...@ccil.org
Is a chair finely made tragic or comic? Is the portrait of Mona Lisa
good if I desire to see it? Is the bust of Sir Philip Crampton lyrical,
epical or dramatic? If a man hacking in fury at a block of wood make
there an image of a cow, is that image a work of art? If not, why not?
--Stephen Dedalus
The design I ended up with was rejected for the original use, but my friend encouraged me to carry on with the design, which has now produced something I've dubbed the PDP-8/X architecture. I'd appreciate any comments: post them here, send them to co...@ccil.org, or post PRs at https://github.com/johnwcowan/pdp8x.
The design document in that repo assumes zero familiarity with the PDP-8. For this audience I can summarize it like this:
* Words and addresses are 32 bits, but instructions are only 16 bits. This means that when (a) the last instruction before a label or (b) a JMS instruction is stored as the first of the two 16-bit instructions in the word, the assembler needs to fix things up by inserting a NOP after the instruction.
* MRI instructions are the same except that the indirect bit has been rotated to bit 0, so that opcodes 0x0 to 0x6 are direct and 0x8 to 8xD are indirect. The resulting page address is 11 bits, so pages are 2KW instead of 128 words, and you can have up to 2M pages or 4 GW (16 GB) of memory. Plenty of room!
* I/O instructions keep the 0x8000, 0x800, 0x80, and 0x8 bits clear, so that TLS, for example, is now 0x6034.
* OPR instructions likewise rotate the group 1 / group 2 bit to bit 0, so that group 1 has an opcode of 0x7 and group 2 an opcode of 0xF. The same bit spacing pattern used for I/O is used, so that CLA CLL is 0x7300. However, rather than squeezing group 3 (standard only, no EAE) into group 2, MQA and MQL are in the 0x80 and 0x8 bits of group 1, which means they can be microcoded together for instructions like CLA CMA MQL.
* The BSW instruction is split into two: HSW to swap half-words ("UNIX" becomes "IXUN") and BSW to swap the individual bytes of each half-word ("UNIX" becomes "NUXI").
Enjoy, and advTHANKSance.
John Cowan http://vrici.lojban.org/~cowan co...@ccil.org
Is a chair finely made tragic or comic? Is the portrait of Mona Lisa
good if I desire to see it? Is the bust of Sir Philip Crampton lyrical,
epical or dramatic? If a man hacking in fury at a block of wood make
there an image of a cow, is that image a work of art? If not, why not?
--Stephen Dedalus
K. Krause
Jun 30, 2020, 12:00:02 PM6/30/20
to
On 26.06.20 05:37, johnw...@gmail.com wrote:
> I cut my teeth on the PDP-8 back in the 1970s, and have had only > a casual acquaintance with it since. But I got a copy of an open
> call from a friend for a "32-bit deterministic integer machine", as
> simple as possible but no simpler. Naturally I thought of the PDP-8
> a word machine can have almost any word size without changing much.
>
In the late 70ies I considered a 24-Bit extension of the PDP-8. I knew
> I cut my teeth on the PDP-8 back in the 1970s, and have had only > a casual acquaintance with it since. But I got a copy of an open
> call from a friend for a "32-bit deterministic integer machine", as
> simple as possible but no simpler. Naturally I thought of the PDP-8
> a word machine can have almost any word size without changing much.
>
the 24-bit ICL 1900 machines and the 24-bit Siemens 300. I also got my
first Intersil-Sampler with the IM 6100.
24 bits sound much more like PDP-8X than 32 bits.
24 bits can be divided in 8-bit bytes and also in 6-bit bytes. Keeping
the relation one-word in one-instruction you get larger page size and
can spend more bits for the opcodes. And an address space of 24 bits
at that time seemed huge enough to be never fully used. (16M words,
not bytes!).
The indirect bit in the MSB of the Siemens 300 allowed multiple
indirect addressing. If it was set, then this address was again used
as indirect address and so on. I believe they had a counter to stop
indirectation after some levels to prevent endless addressing loops.
Other (16-bit)-extensions of the PDP-8 architecture are the hp 2216
and the DG nova.
Klemens
John Cowan
Jul 2, 2020, 4:19:57 PM7/2/20
to
On Tue, Jun 30, 2020 at 12:00 PM K. Krause <klemens...@gmx.net> wrote:
Thanks for the review!
> In the late 70ies I considered a 24-Bit extension of the PDP-8.
That's a very interesting idea, but I think the time for machines whose word size is not a power of two has passed, so I'm sticking with 32 bits. However, I have switched from byte addressing back to word addressing, while keeping the "two instructions per word" format.
This complicates the fetch-decode-execute cycle somewhat: there needs to be a 1-bit internal register to keep track of which halfword will be executed next, and the assembler must insert NOP padding to make sure that a JMS is always in the second halfword and a JMP target always in the first halfword. (The latter will break if attempt to modify a JMP instruction on the fly, of course.)
> I knew
> the 24-bit ICL 1900 machines and the 24-bit Siemens 300. I also got my
> first Intersil-Sampler with the IM 6100. Other (16-bit)-extensions of the PDP-8 architecture are the hp 2216 and the DG nova.
I know the Nova. I'll look into the other machines when I get a chance.
> The indirect bit in the MSB of the Siemens 300 allowed multiple
> indirect addressing. If it was set, then this address was again used
> as indirect address and so on. I believe they had a counter to stop
> indirectation after some levels to prevent endless addressing loops.
I've never been a fan of invisible pointers, even with a looping check. They have a few very particular applications, but most of the time they just require extra logic that will rarely be used.
You are a child of the universe no less than the trees and all other acyclic
graphs; you have a right to be here. --DeXiderata by Sean McGrath
Thanks for the review!
> In the late 70ies I considered a 24-Bit extension of the PDP-8.
This complicates the fetch-decode-execute cycle somewhat: there needs to be a 1-bit internal register to keep track of which halfword will be executed next, and the assembler must insert NOP padding to make sure that a JMS is always in the second halfword and a JMP target always in the first halfword. (The latter will break if attempt to modify a JMP instruction on the fly, of course.)
> I knew
> the 24-bit ICL 1900 machines and the 24-bit Siemens 300. I also got my
I know the Nova. I'll look into the other machines when I get a chance.
> The indirect bit in the MSB of the Siemens 300 allowed multiple
> indirect addressing. If it was set, then this address was again used
> as indirect address and so on. I believe they had a counter to stop
> indirectation after some levels to prevent endless addressing loops.
You are a child of the universe no less than the trees and all other acyclic
graphs; you have a right to be here. --DeXiderata by Sean McGrath
K. Krause
Jul 3, 2020, 11:00:02 AM7/3/20
to
On 02.07.20 22:19, John Cowan wrote:
> On Tue, Jun 30, 2020 at 12:00 PM K. Krause <klemens...@gmx.net> wrote:
...
> On Tue, Jun 30, 2020 at 12:00 PM K. Krause <klemens...@gmx.net> wrote:
>> In the late 70ies I considered a 24-Bit extension of the PDP-8.
>
> That's a very interesting idea, but I think the time for machines whose word size is not a power of two has passed, so I'm sticking with 32 bits. However, I have switched from byte addressing back to word addressing, while keeping the "two instructions per word" format.
That was in the mid 1970ies. The first 16-Bit microprocessors were
>
> That's a very interesting idea, but I think the time for machines whose word size is not a power of two has passed, so I'm sticking with 32 bits. However, I have switched from byte addressing back to word addressing, while keeping the "two instructions per word" format.
visible at the horizont. And the large scale computer at the university
here in Stuttgart, the TR440 hat 256K Words of 48(52) Bits.
>
> This complicates the fetch-decode-execute cycle somewhat: there needs to be a 1-bit internal register to keep track of which halfword will be executed next, and the assembler must insert NOP padding to make sure that a JMS is always in the second halfword and a JMP target always in the first halfword. (The latter will break if attempt to modify a JMP instruction on the fly, of course.)
>
computer an architecture which keeps things simple. THe most attractive
idea in that project was, to be compatible to the PDP-8 on assembly
level, not at binary level. But naturally if memory-structure has more
words for example in zero page and page size generally, than naturally
all address computation has to be adapted individually and simply
reassembly of the original FORTRAN-compiler is impossible.
>> I knew
>> the 24-bit ICL 1900 machines and the 24-bit Siemens 300. I also got my
>> first Intersil-Sampler with the IM 6100. Other (16-bit)-extensions of the PDP-8 architecture are the hp 2216 and the DG nova.
>
> I know the Nova. I'll look into the other machines when I get a chance.
>
end of GDR (east germany) I was in an electronic surplus store in east
Berlin. Don't remember if that was after the reunion or nearly before.
In this shop I fond three east-german bitslice ICs: U830C. The only
8-bit bit slices I've ever seen. People say that they were intended to
make an east german PDP11.
I bought them all, and so the idea of the 24-bit PDP-8 came up again.
But at that time I had no documentation for them, the project is stopped
until today.
KLemens
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