Any news on David Conroy's PDP-10 clone?

[David G. Conroy]

Last time I posted, I was running ITS, with new drivers for modern (16c450
console, ATA disk) emulated peripherals, on the high-level model
(micromachine register-level emulation, emulating the real microcode).

I've been very busy with other things (both work related and non-work
related), but I'm pretty much at this state on a low-level model (registers
and control equations) as well. Most of the work getting to this state was
redesigning the micropipeline, taking time from the ALU and giving it to the
AC RAM address calculation and read access (the former is pretty complicated
since it needs to deal with PXCT various +N operations). There are still
three microinstructions in flight at the same time, but I did need to add a
bypass for the micro-condition-codes so that a branch right after an ALU
operation got to use the *new* codes (a similar case already existed for the
EA<20 check to avoid needed a hazard-avoiding NOP in the main indirect
address calculation flow).

Recently I been thinking about packaging, and looking at some routing and
signal integrity issues, mainly on the 32Kx8 SRAMS which make up the control
store.

dgc