developping a simple PC-card (conforming to PCMCIA 2.1, I hope) with
two devices (functions), first standard I/O (it will be 16C550) and
the second with memory-mapped I/O (one '51-styled periph with data/
addr mux resolved by A0). I have several questions, which I have not
been able to resolve from freely available docs.
First, I wanted to avoid CPLD (I like them, but not for such simple
task). On the other hand, it seems, that world is cruel and management
stupid, so for active development, ICs like PCM16C00 are not
perspective. Because the functionality I need seems to me to be
absolutely trivial, I would like to solve it on standard logic (74..)
basis. For the attribute memory, I'd like to employ standard parallel
ROM (EEPROM, FLASH).
My questions are:
* can I safely ignore (not connect) CE2# pin, if both devices have 8-
bit data bus? (suppose yes)
* can I hardwire IOIS16# directly to Vcc? (suppose yes)
* can I hardwire INPACK# directly to the IORD#?
* can I leave A0 not connected to the attribute memory? (suppose yes,
since only the
even addrs are used in CIS)
* is it required to gate IORD# (IOWR#) with either REQ# or CE*#
signals??? However, this is rather philosophical question, because
(REQ# + CE1#) will be evaluated as a CE# for the attribute memory
already; (accorgind to diagrams and CompactFlash specs, it should not
be needed to gate them, but chips like PCM16C010 do that and also
SanDisk HW development guide tells, that gating of IORD/WR# by REQ#
low is required)
* can I decide to use level-sensitive interrupts in the design without
any explicit care about the host system? Is it possible to "OR"
interrupt requests from both I/O devices to one resulting IREQ# line?
And two more general questions, concerning future compatibility:
* can I get 5V supply in every PCMCIA compliant slot? Or, does some
slots provide only 3V3 supply?
* will any CardBus compliant host work with "old" 16-bit PC-card?
Thank you very much for any answered question.
Marek Peca <m...@duch.cz>