On Sun, 22 Jul 2018 22:48:03 -0700 (PDT)
Paul Edwards <
muta...@gmail.com> wrote:
> On Sunday, 22 July 2018 04:03:25 UTC+10, Rod Pemberton wrote:
>
> I'm not sure I understand your question,
> but in my OS I leave the 1 MiB to 2 MiB
> region untouched, to allow for the
> possibility of the A20 line not being
> enabled. So I only start allocating
> ATL memory at 2 MiB.
Ah, Ok.
After rereading your posts a few times, I just figured out why we're
talking at cross purposes ... (at bottom).
> This means that if
> my command processor and application are
> fairly small, both fitting in to 1 MiB,
> then I will not go above 3 MiB which is
> where the A20 address wrapping occurs
> (again, but this time unavoidable).
>
***IF*** entering PM with A20 disabled is valid, that should be fine, I
would think.
> Thanks for your other info about the
> A20 line, I'll try switching technique.
>
You're viewing the A20 line as an actual processor address line, like
on the early 8086 to 80486 processors. So, you're viewing memory - with
A20 DISABLED - as having "gaps" in memory above 1MB due to wrap every
other megabyte. I.e., from 1MB to 2MB wrapping to zero, but 2MB to 3MB
is present, 3MB to 4MB wrap to zero, 4MB to 5MB is present, etc. Yes?
I thought you were saying you had a wrap issue at 3 MiB with A20
ENABLED, where memory should be flat, no wraps or gaps ... So, this is
not a wrapping issue with A20 enabled, e.g., top of memory or coding
error, as I was thinking. I.e., I was thinking the emulator was
limited to 4 MiB or some such, and you were reaching the top of
physical memory at 3 MiB virtual, etc.
A20 probably still works that the way it historically did, i.e.,
linear memory gaps due to wrap when A20 is disabled. I've never checked
this. Nowadays, I don't think of A20 working as it would electrically
on a schematic. I usually think of A20 disabled as blocking all access
to memory above 1MB until A20 is enabled.
My question now is how are you accessing memory above 1MB physical? RM
segment:offset addressing only goes to 1MB+64KB+16. I.e., to load your
app to 2 MiB PM must be enabled (or a BIOS call using PM must be used)
or unreal mode (pop into PM and change hidden segments limits for RM).
Are you entering PM without A20 being enabled? Just a reminder, you
can't enable or disable A20 once in PM:
"When A20M# is sampled asserted in Protected mode, it causes
unpredictable processor operation. A20M# is only defined in Real Mode."
I'm not sure what effect, if any, that entering PM with A20
disabled has, or if that's also undefined or unpredictable.
One processor (Intel Atom) has an errata that says it has problems with
2MB/4MB pages when A20 is disabled (and some other conditions). Uh, ...
yeah. I would assume that A20 is enabled before entering PM prior to
enabling paging, usually. So, I'm not sure what is going on there.
The notes on the archived page show some machines have A20 enabled by
default after boot up, "Boot-Time A20". There is a 2001 Microsoft
specification that requires that A20 is always on, i.e., "Legacy-Free
Hardware and BIOS Requirements." And, I seem to recall that there is at
least one processor which automatically enables A20 upon entering PM,
but I can't seem to find it ...
Sorry about my confusion (or perhaps yours).