6502

[muta...@gmail.com]

I used to program on the Commodore 64, which used
the 6510 (basically 6502), and I recently realized that
the way it used a pair of 8-bit values to access memory
makes it fundamentally segmentation not much
different to the 8086.

(I think).

Anything preventing using 4 8-bit values to access
4 GiB of memory instead of 64k?

Would that be useful in any situation, given that I
believe people still program 8-bit CPUs?

Thanks. Paul.

[Alexei A. Frounze]

On Sunday, November 27, 2022 at 12:06:47 AM UTC-8, muta...@gmail.com wrote:
> I used to program on the Commodore 64, which used
> the 6510 (basically 6502), and I recently realized that
> the way it used a pair of 8-bit values to access memory
> makes it fundamentally segmentation not much
> different to the 8086.

Not quite. There's only one special "segment", the "zero page".
It can be accessed using an implicit segment 0, that is, address bits
15 through 8 are all zeroes.
OTOH, if you use the indirect-Y addressing mode, you're almost
using a GDT. That is, the zero page can contain up to 128 16-bit
addresses and you can choose one of them and add an 8-bit
offset to those 16 bits.

Alex

[anti...@math.uni.wroc.pl]

In short, you can. Slightly longer: I already mentioned
STM8. It is 8-bit processor similar in spirit to 6502.
But it allows 24-bit addresses, that is access to 16M
of memory. They did not support 32-bit addresses, but
that is really question of need. 24-bit addresses are
used to break 64k barier, which is important for small
processors. OTOH nobody makes such small processors
with more than 2M of memory, so 16M is really not
limiting.

Concerning segmentation: there is important difference,
in 6502 nas STM8 when you want you can use long addresses
giving you flat address space (without need for extra
code to nomalize pointers in huge model). And when it
is enough you use shorter addresses. Much easier for
programmer or compiler than 8086 segmentation.

--
Waldek Hebisch

[muta...@gmail.com]

On Monday, November 28, 2022 at 9:18:18 PM UTC+8, anti...@math.uni.wroc.pl wrote:

> Concerning segmentation: there is important difference,
> in 6502 nas STM8 when you want you can use long addresses
> giving you flat address space (without need for extra
> code to nomalize pointers in huge model). And when it
> is enough you use shorter addresses. Much easier for
> programmer or compiler than 8086 segmentation.

If the 8086+ had 16-bit segment shifts instead of 4,
would that still be considered segmentation, or
would it be considered flat like the 6502?

Thanks. Paul.

[anti...@math.uni.wroc.pl]

It would be important step towards flat address space.

To say more: important part of judging architecure is how
well various parts fit together. In segmented architecure
when you add offsets and result is bigger than segment you
expect exception (in good segmented architecure) or maybe
wraparound within segment (like in 8086). In flat mode,
even if address is split between two registers one expect
that adding offset will propagate carry to higher part.
Such carry propagation may be done by single instruction
operating on register pair (like in 8080), or could be
split into say two instructions. But to say that there
is flat address space this should be resonably convenient.
In 8086 having to move segment register to general
purpose one for arithmetic and back to segment register
for actual access would look as particularly incovenient
given that all general purpose register can take
part in arithmentic and there are instructions operating
one register pairs.

Maybe example could help: AVR processor are 8-bit ones,
having 32 registers. 3 register pairs can be treated
as 16-bit address registers. IIUC to load constat
address or address from memory you need two separate
instructions, one for each register int the pair. Similarly,
if you want to add 16-bit offset stored in some other two
register to an address you need two instructions. This
looks resonable, because this is 8-bit processor and
handles only 8-bits in single operation. OTOH, there
are "indexed" load and store instructions: instruction
provides 8-bit constant offset and this offset is added
to address in register pair and result of addition
is used as memory address. In this operation address
addition is effectively done as 16-bit operation, that
is propagates carry to higher bits. Not propagating
carry would effectively break flat address space.
As extra remark: this "indexed" load is what is needed
to access members of C struct when pointer to struct
is loaded to address register. So this is pretty
important instruction for C compiler.

--
Waldek Hebisch