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Clock multiplier circuit
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Spaced Cowboy
Oct 4, 2017, 11:37:02 AM10/4/17
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Hi :)
First off, I'm not a hardware engineer, I work with FPGAs and verilog, coupled with firmware code generally. I have, however found http://opencircuitdesign.com and I'm looking at trying to build my own ASIC, just for the pure fun of it. Part of that fun is learning new things ...
The application I have in mind, and for which I've written the verilog, is a neural network "processor", with a SPI interface for data. I'll be hopefully implementing it in 180nm (yes, I know, very old tech, but I'm using free tools here, and that's as high-res as the easily-accessible technology files go), and hobbyist-friendly shuttle runs need to be (relatively) cheap...
So, I'm using Magic to do the layout fine tuning (pads, non-verilog requirements etc.), with Yosys to get the standard cell structure in the first place from the HDL, and I obviously want it to run as fast as possible. I have no real idea how fast I can input a clock into a 180nm chip at 3.3v, but I doubt I can just feed a 250 MHz input in... I was thinking I could try and multiply a lower-speed clock internally. I'm fine with it being something simple (x4 or similar) and there's nothing thats timing-critical in the implementation, so it doesn't have to be temperature-stable, and it can vary around the desired frequency if it has to. I just want to be able to run the internals much faster than the external clock.
It was suggested to me that a ring oscillator might be a solution, but on its own I don't think one of those would be fast enough - the papers I've been reading seem to top out at ~36MHz or so (from a constant input). I'm not sure if I could just feed in a clock to such an oscillator, but it seems to me the time-constant of the oscillator would still be the limiting factor, even if the input is varying and not constant.
So, anyone want to point me in the right direction for a "idiot's guide to designing a clock multiplier". Is there a college course online or a worked example in a book somewhere ?
Thanks for any help :)
First off, I'm not a hardware engineer, I work with FPGAs and verilog, coupled with firmware code generally. I have, however found http://opencircuitdesign.com and I'm looking at trying to build my own ASIC, just for the pure fun of it. Part of that fun is learning new things ...
The application I have in mind, and for which I've written the verilog, is a neural network "processor", with a SPI interface for data. I'll be hopefully implementing it in 180nm (yes, I know, very old tech, but I'm using free tools here, and that's as high-res as the easily-accessible technology files go), and hobbyist-friendly shuttle runs need to be (relatively) cheap...
So, I'm using Magic to do the layout fine tuning (pads, non-verilog requirements etc.), with Yosys to get the standard cell structure in the first place from the HDL, and I obviously want it to run as fast as possible. I have no real idea how fast I can input a clock into a 180nm chip at 3.3v, but I doubt I can just feed a 250 MHz input in... I was thinking I could try and multiply a lower-speed clock internally. I'm fine with it being something simple (x4 or similar) and there's nothing thats timing-critical in the implementation, so it doesn't have to be temperature-stable, and it can vary around the desired frequency if it has to. I just want to be able to run the internals much faster than the external clock.
It was suggested to me that a ring oscillator might be a solution, but on its own I don't think one of those would be fast enough - the papers I've been reading seem to top out at ~36MHz or so (from a constant input). I'm not sure if I could just feed in a clock to such an oscillator, but it seems to me the time-constant of the oscillator would still be the limiting factor, even if the input is varying and not constant.
So, anyone want to point me in the right direction for a "idiot's guide to designing a clock multiplier". Is there a college course online or a worked example in a book somewhere ?
Thanks for any help :)
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