7820X
2066 Core i7 i7-7820X(U0) Skylake-X 3.6GHz 11MB 140W lanes=28
Slot x16_3 doesn't work with a 28-Lane CPU (page 1-8)
Only a 44-Lane CPU has all (big) slots working.
The manual isn't clear as to how the smaller
slots are provisioned. Some can come off the PCH (X299).
The PCH I/O is provisionable. Which means they can use
some wires from X299 as SATA or PCIe, when designing the thing.
That suggests the small slots might work all the
time, that's if they did a good job. The PCH has as
many as 24 lanes. Three M.2 slots would be 12 lanes.
x4,x4,x1 PCIe slots would use 9 lanes. That leaves
3 lanes left. The LAN port might take a lane.
The USB3 Gen2 might take two lanes (if done with
an external chip).
If you download the X299 datasheet, there's probably
a table of how the wiring can be juggled to do all that.
USB3 connectors have 9 pins. Four of the pins are
USB2 pins, if it matters. You can still plug
USB2 devices into a USB3 connector.
And it's a good question, what kind of controls
exist for PCIe disablement. I don't have any
NVMe capable systems here to play with, to see.
Section 3.6.7 in the manual, shows complicated
interactions between slots.
PCIEX4_1 and PCIEX16_3 (on a 28-lane CPU, maybe
neither work???)
PCIEX1 and U31G2_E3 (lane sharing, either/OR)
SATA78 and PCIEX4_2 (lane sharing, either/OR)
Looks like a plate-ful of HEDT manual reading.
Paul