How to generate ISA 16 bits IOCS16 signal ?
Philippe Jung
Hi,
I am developping extension board for a PC motherboard in order to make a
robot. But I don't understand how and when to generate the IOCS16 signal
for the ISA bus. Could you help me ?
Thanks.
=========================================================
Philippe JUNG (Philip...@Supelec.fr)
4 Place Edouard Branly, 57070 METZ, FRANCE
http://www.ese-metz.fr/~jung/
COMPUTERCRAFT
The PC HARDWARE FAQ in the REFERENCE section of COMPUTERCRAFT might
offer some tips.
--
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ao...@computercraft.com
14 Center Street, Jersey City, NJ 07302
201-795-0909
fax: 201-985-8399
Re-Elect Bret Schundler Mayor Of Jersey City
http://www.mayorschundler.com
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gre...@concentric.net
In <01bc5274$f3f7ab70$01e130c1@snoopy>, "Philippe Jung" <Philip...@supelec.fr> writes:
>Hi,
>
>I am developping extension board for a PC motherboard in order to make a
>robot. But I don't understand how and when to generate the IOCS16 signal
>for the ISA bus. Could you help me ?
>
>Thanks.
>
You will have an address decoder circuit connected to
A1 to A15. WHen this decoder detects a valid address;
one that will strobe your IO registers; it should generate
the IOCS16 signal. be sure that you use an active low
open collector gate to drive IOCS16 onto the bus.
It is not necessary to qualify the decoded address select
with IORD or IOWR.
Hope this helps.
====================================
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====================================
Håkan Mattsson
gre...@concentric.net wrote:
>
> In <01bc5274$f3f7ab70$01e130c1@snoopy>, "Philippe Jung" <Philip...@supelec.fr> writes:
> >Hi,
> >
> >I am developping extension board for a PC motherboard in order to make a
> >robot. But I don't understand how and when to generate the IOCS16 signal
> >for the ISA bus. Could you help me ?
> >
> >Thanks.
> >
>
> You will have an address decoder circuit connected to
> A1 to A15. WHen this decoder detects a valid address;
> one that will strobe your IO registers; it should generate
> the IOCS16 signal. be sure that you use an active low
> open collector gate to drive IOCS16 onto the bus.
> It is not necessary to qualify the decoded address select
> with IORD or IOWR.
>
> Hope this helps.
>
are 8 bits wide you should not assert IOCS16.
--
Håkan
arnbel
Upon decoding the address, turn on a npn transistor (limiting the base
currant with 1k) and connect the collector to CS16. It will pull the bus
down, telling the bus controller to put all 16 bits of data on the line for
this transaction. It is important to do this as quickly as possible,
Arnold Beland
Philippe Jung <Philip...@supelec.fr> wrote in article
<01bc5274$f3f7ab70$01e130c1@snoopy>...
>
> Hi,
>
> I am developping extension board for a PC motherboard in order to make a
> robot. But I don't understand how and when to generate the IOCS16 signal
> for the ISA bus. Could you help me ?
>
> Thanks.
>
Nino Benci
I have used a 74LS126 tristate buffer. EN to your generated CSIO16 signal, D
to ground and O to the /CSIO16 line on the AT bus. This works very well and
being a tristate output has no problems with other OC devices connected to
the /IOCS16 line.
arnbel
arnbel wrote:
>
> Upon decoding the address, turn on a npn transistor (limiting the base
> currant with 1k) and connect the collector to CS16. It will pull the bus
> down, telling the bus controller to put all 16 bits of data on the line
for
> this transaction. It is important to do this as quickly as possible,
>
> Arnold Beland
All 16 bits are already on the bus. The signal CSIO16 tells the bus
controller that all 16 bits have been received. If the IOCS16 signal
does NOT come the bus controller will send the most significant 8 bits
(8-15) again, at address+1, at data lines 0-7.
--
Håkan
Hi Hakan (I don't think that I have one of those funny things to put above
the first a.
I have always used MEMCS16 for data transfers and assert CS16 upon
latching the address. I started doing this when the AT bus first appeared.
The bus timing diagrams I have all show a considerable amount of time
between the assertion of CS16 (which I know from painful experience has to
be ASAP after ALE) and the Data Valid window (within which MEMW or IOW
rising edge must occur). So, given the way an individual instruction
works, (get the data then send it), the 16 bits are in the CPU register.
But, are the 16 bits that are on the bus at ALE these bits or data left
over from the previous instruction? You may very well be correct. The
beauty of using PC motherboards as controllers is in not having to know
exactly what is going on inside them. What the hell, I'm not making life
support systems.
Regards,
Arnold Beland
PS I tried to email you but I could not figure out how to take the nospam
part out.
I am new to all this on line stuff. I appreciate the fact that you emailed
me to correct my statement but it is not necessary, my ego is secure.
----------
gre...@concentric.net
In <01bc5518$82e764b0$7700a8cb@p120>, "arnbel" <arn...@webquest.com> writes:
>arnbel wrote:
>>
>rising edge must occur). So, given the way an individual instruction
>works, (get the data then send it), the 16 bits are in the CPU register.
>But, are the 16 bits that are on the bus at ALE these bits or data left
>over from the previous instruction? You may very well be correct. The
>beauty of using PC motherboards as controllers is in not having to know
>exactly what is going on inside them. What the hell, I'm not making life
>support systems.
>
>Regards,
>
>Arnold Beland
>
Two points here;
1- We were talking about IOCS16 not MEMCS16. One is for
IO cycles the other is for memory cycles.
2- Getting a bit off topic (sorry). When AEN goes active, the
address lines will have valid address information. The data
bus could have anything. The data bus is valid at the trailing
edge of either of the IOWR or MEMWR strobes. Note that
the data bus isn't even garenteed to be valid on the leading edge
of these strobes. I have seen this little fact chomp a few
engineers in the butt.
arnbel
> Perhaps I have been working alone for too long. Rising to me means from
neg to pos. The write signals on the ISA bus are a pull down to ground.
To me, a pulse is a pulse and the word does not imply a certain duty
cycle. Am I getting sloppy in my use of language in my old age? If so,
tell me. I can take it.
Arnold
Håkan Mattsson
arnbel wrote:
>>
>> arnbel wrote:
>> >
>> > Upon decoding the address, turn on a npn transistor (limiting the base
>> > currant with 1k) and connect the collector to CS16. It will pull the bus
>> > down, telling the bus controller to put all 16 bits of data on the line
>> > for this transaction.
>>
>> All 16 bits are already on the bus. The signal CSIO16 tells the bus
>> controller that all 16 bits have been received. If the IOCS16 signal
>> does NOT come the bus controller will send the most significant 8 bits
>> (8-15) again, at address+1, at data lines 0-7.
>>
> Hi Hakan
Snip
> But, are the 16 bits that are on the bus at ALE these bits or data left
> over from the previous instruction? You may very well be correct.
>
With my "All 16 bits are already on the bus" I meant that IOCS16 does
not tell the controller to put 16 bits on the bus, it's the running
software that makes that choice.
If IOSC16 is sent, the bus controller knows that it has written/read 16
bits, and if _not_ IOCS16 is sent the bus controller understands that
there is an 8-bit device out there, adds 1 to the address and
a) if read: reads again from bits 0-7 to get the data it really wanted
from bits 8-15, or
b) if write: puts the data it tried to write earlier (at bits 8-15) out
again at bits 0-7 and writes again.
PS I've seen motherboards (-286, -386 and -486) perform this action even
though IOCS16 _has_been_ sent, so first it has performed a 16 bit
access, and after that an unnecessary 8-bit access asswell!
--
Håkan
Keith R. Williams
arnbel wrote:
>
> > Perhaps I have been working alone for too long. Rising to me means from
> neg to pos.
No, it *should* be defined as a '0' to '1' transition. THe definition
of
'0' and '1' are left to the engineer, which is ISA's biggest anchor
(the
engineers blew it).
----
Keith
arnbel
Keith wrote:
No, it *should* be defined as a '0' to '1' transition. THe definition
of
'0' and '1' are left to the engineer, which is ISA's biggest anchor
(the
engineers blew it).
----
Keith
So, with the ISA BUS, we use POS LOGIC to describe the data and address
lines and NEG LOGIC for the control lines. No wonder people are still
using PORT OUTS>
arnbel
Keith R. Williams <k...@ibm.net> wrote in article <337138...@ibm.net>...