Kudos to Lyric Semiconductor for a truly forward-looking idea, but
poor marks for the editors at MIT's Technology Review and author
(journalist?) Tom Simonite, whose definition of the logic of a NAND
gate is NOT conventional: "a conventional NAND gate outputs a 1 if
neither of its inputs match." Nope, that's a (NOT XOR) gate. I think
we would all agree that a conventional NAND gate outputs a 1 iff
either of its inputs is 0.
Having clarified that, now consider the description of the new
probabilistic NAND gate: "...the output of a Bayesian NAND gate
represents the odds that the two input probabilities match..."? Recall
that in inferential statistics, all you may do is compute the
confidence that the NULL hypothesis (H0) may be REJECTED, or (if you
dare) SPECULATE about the acceptance of the alternative (remember
those dastardly ubiquitous Type II errors?). In general, to be on the
safe side, it is generally safer to "reserve judgement."
With that correction, how do we assert H0 so that a sufficient
statistical confidence that H0 may be rejected leads to a reasonable
conclusion that "the output of a Bayesian NAND gate represents the
odds that the two input probabilities match"? I cannot quite connect
the dots here.
Finally, what on earth does this have to do with Bayes?
Am I missing something here?