Does sst-gem5-2.2 support ARM?

[fernand...@gmail.com]

Hello,

I would like to know if the package sst-gem5-2.2.tar.gz supports ARM_SE, because it fails to compile.

Thanks for help,

Fernando

[Simon Hammond]

Not yet. Something we're looking into but we have tailored our
existing simulation capabilities for x86. To be honest most of our
experience is showing the ISA isn't hugely important in most of our
studies (since we can tailor the details of the core to be more
ARM-like).

If this is of interest then let us know, its something we could
consider including in future work.

--
Si Hammond

[Ben Payne]

Hello,

Is this still the current stance for SST 3.0?

I don't have any specific ISA requirements yet, but I could foresee requesting ARM support. Probably the other capabilities (multiple compute nodes, parallelization) are more important in the meantime.

Thank you,

Ben

[Simon Hammond]

This is still the position but we have not actively tested whether this does or does not work yet. Taking a guess I could see us just trying to rebuild our SST-GEM5 with the ARM-ISA, cross-compiling the applications and attempting a run.

If you think this is important we can bump (at least trying this) up the priority chain.


S.

--
Simon Hammond
Scalable Computer Architectures (CSRI/146, 01422)
Sandia National Laboratories, NM, USA

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[Ben Payne]

As I mentioned earlier, this is lower priority than the other goals (multi-core CPU running in parallel, multiple nodes).

To test out whether ARM would work, on CentOS 6.4 64bit I installed SST 3.0 and gem5 x86. I tested these with "hello.c" and it works as expected.

Below is what I get when I attempt to build the gem5 library for ARM:

[bpayne@ben-virtual-centos64 sst-gem5-3.0.0]$ pwd
/home/bpayne/sst/scratch/src/sst-gem5-3.0.0

[bpayne@ben-virtual-centos64 sst-gem5-3.0.0]$ vi build/variables/ARM

TARGET_ISA = 'arm'
CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'

[bpayne@ben-virtual-centos64 sst-gem5-3.0.0]$ scons build/ARM/libgem5_opt.so
scons: Reading SConscript files ...
Checking for leading underscore in global variables...(cached) no
Checking for C header file Python.h... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking for C library python2.6... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached) yes
Checking for C header file fenv.h... (cached) yes
Reading SConsopts
Building in /home/bpayne/sst/scratch/src/sst-gem5-3.0.0/build/ARM
Using saved variables file /home/bpayne/sst/scratch/src/sst-gem5-3.0.0/build/variables/ARM
scons: done reading SConscript files.
scons: Building targets ...
[ SHCXX] ARM/base/atomicio.cc -> .os
[ SHCXX] ARM/base/bigint.cc -> .os
[ SHCXX] ARM/base/bitmap.cc -> .os

..<snipped by Ben>..

[ SHCXX] ARM/python/swig/debug_wrap.cc -> .os
[ SWIG] ARM/python/swig/event.i -> _wrap.cc, .py
In file included from build/ARM/sim/os.hh:7,
from build/ARM/sim/simulate.cc:41:
build/ARM/arch/x86/registers.hh:45:37: error: arch/x86/max_inst_regs.hh: No such file or directory
In file included from build/ARM/sim/os.hh:7,
from build/ARM/sim/simulate.cc:41:
build/ARM/arch/x86/registers.hh:50: error: 'X86ISAInst' has not been declared
build/ARM/arch/x86/registers.hh:51: error: 'X86ISAInst' has not been declared
In file included from build/ARM/sim/simulate.cc:41:
build/ARM/sim/os.hh:64: error: 'ArmISA' has not been declared
scons: *** [build/ARM/sim/simulate.os] Error 1
scons: building terminated because of errors.

Even with my two line build/variables/ARM file added, it looks like ARM won't work without some tweaking, but I'm not sure how significant the changes would be.

Unless the changes needed are minor, I'm not looking for progress on more ISAs being supported for at least the summer.

Ben

[Hammond, Simon David (-EXP)]

Ok thanks for the info, I'll see what we have our side.

S



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[Kelly, Suzanne M]

> Below is what I get when I attempt to build the gem5 library for ARM:
> [bpayne@ben-virtual-centos64 sst-gem5-3.0.0]$ pwd

Does the Gem5 trunk not have this problem? Is it because the SST Gem5 source is out of date? The SST team would have to re-integrate with a later Gem5 if that's the problem.

Sue

[Hammond, Simon David (-EXP)]

We need to look into this some more to be sure, the ARM stuff is very actively developed so we may be a reasonable way behind :(.

--
Simon Hammond
Scalable Computer Architectures (Org. 01422)
Sandia National Laboratories, NM
[Sent from remote connection, please excuse typing errors]

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From: SST-si...@googlegroups.com [SST-si...@googlegroups.com] on behalf of Kelly, Suzanne M [smk...@sandia.gov]
Sent: Tuesday, June 04, 2013 11:24 AM
To: SST-si...@googlegroups.com

[Fernando Endo]

Hello,

I'm very interested in SST supporting ARM. I'm currently working with gem5 and McPAT, so as we know the temperature is important now.

That would be great! If you need people to test, feel free to ask me.

Regards,

--
Fernando A. Endo, PhD student and researcher

Université de Grenoble, UJF
France

2013/6/4 Hammond, Simon David (-EXP) <sdh...@sandia.gov>