aarch64 ASIMD instruction decode

[Alireza Khadem]

Hi All,

I am developing a client to dump dynamic instruction traces of specific functions.

Everything works fine but I don't know how to detect ASIMD instructions and their precisions. Here is an example:

Consider scalar double-precision floating-point multiplication:
double c, a, b;
c = a * b;

The assembly is this: 
FMUL Dd, Dn, Dm

What Dynamorio gives me is this (which is correct):
FMUL Dd, Dn, Dm

Now consider ASIMD 2 single-precision floating-point multiplication:
float32x2_t c, a, b;
c = vmul_f32(a, b)
The assembly is this:
FMUL Vd.2S,Vn.2S,Vm.2S
What Dynamorio gives me is this (which is the scalar floating-point representation): 
FMUL Dd, Dn, Dm

Which could be the output for 4 half-precision floating-point too:
FMUL Vd.4H,Vn.4H,Vm.4H

In other words, I couldn't find a way to detect the precision of a register. Here are the APIs I've used:

To decode the opcode:
const char *decode_opcode_name(int opcode);
To decode the registers:
const char *get_register_name(reg_id_t reg);

Is there any way to detect the precision of an ASIMD operation?

Best,

- Alireza

[Alireza Khadem]

A quick search in this group's history gives me this conversation from 2019:

https://groups.google.com/g/dynamorio-users/c/HekXslaSo98/m/TPpA2cx0EQAJ

I can't believe this feature is not implemented for aarch64! Does anyone know anything about this?

[Joshua Warburton]

Hey Alireza,

I'm Josh and I work on the aarch64 decoder with arm.

In this case vector and non-vector versions of simd instructions can be differentiated by the presence of an extra source operand that is related to the element size.
FMUL Dd, Dn, Dm
would be 
fmul %d %d -> %d

whereas 

FMUL Vd.2S,Vn.2S,Vm.2S
would be
fmul %d %d 0x02 -> %d

For SVE and later instructions, there is a vector element type that directly differentiates operands.

Hope this helps, 
Josh

[Alireza Khadem]

Hi Joshua,

Thanks for your response. What does this 0x02 mean? Would you please confirm that my understanding is correct?

Based on my understanding, to detect vector and float instructions, I should first see if there is any src SIMD register (with reg_is_simd).

Then, I find the register's types (B, H, S, D, Q). In the case of Vn.2S, it would be D.

Then, I find the element size of source registers using that additional immediate int source operand.

Based on my understanding, the coding would be like this (2-bit operand -> element type):

0x00 -> B

0x01 -> H

0x02 -> S

0x03 -> D

0x04 -> Q

In case the register's types = element type, the instruction is floating-point.

In case the register's types > element type, the instruction is ASIMD.

In addition, do we have this additional element size operand for ALL FP/ASIMD instructions?

Best,

- Alireza

[Alireza Khadem]

I have an additional question too.

If the instruction has multiple src/dst registers, which element size this immediate operand does refer to?

For example, SADDW Vd.8H,Vn.8H,Vm.8B has both H and B source elements.

If it refers to the dst register, what about those instructions (like store) that has no destination register?

Best,

- Alireza

[Joshua Warburton]

Hey Alireza,

The rule we used to add these sizes is that the size always refers to the first source register, unless there are no source registers, in which case it refers to the first destination register and it is always the last source operand.

The size is present when there is a simd vector so instructions with only floating points will not have a size operand.

All the best,
Josh

[Derek Bruening]

Is this in the documentation, or we're waiting to decide whether to apply the element size field to the older instructions?

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[assad.hashm...@gmail.com]

> Is this in the documentation, or we're waiting to decide whether to apply the
> element size field to the older instructions?

Sadly it's not documented anywhere yet! We're not planning to apply the element
size field to the older v8.0 and v8.2 instructions. Is there a global IR
document which we can put this sort of thing in? Or do we update the functions'
Doxygen headers so it's generated for each function?

[Derek Bruening]

There is a section on the IR in the docs.  And it seems to already have some content here: https://dynamorio.org/API_BT.html#sec_IR_AArch64

To view this discussion on the web visit https://groups.google.com/d/msgid/dynamorio-users/22663fe6-23b8-4255-8571-a6da5c4897e7n%40googlegroups.com.

[Assad Hashmi]

That's good! I completely missed that IR page! We will update it.