Verification FPGA Design Engineer - San Jose, CA

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Jayan Chhaya

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Feb 10, 2012, 10:09:09 PM2/10/12
to CAREERS AT HCL AMERICA
Job Title: Verification FPGA Design Engineer (2 Positions) 
Location: San Jose, CA 

Qualifications: 
- BSEE required, MSEE preferred 
- A minimum of 4 years experience in a module and system level verification 
- Experience in Test planning, Test case development, simulation etc. 
- Experience in Test environment development 
- Good experience in System Verilog and associated methodologies viz. OVM/UVM 
- Knowledge of system I/O protocols such as SATA, SCSI, or SAS desired 
- Familiar with memory systems such as FLASH/ONFI desired 

Description: 
- Responsible for module/system level test planning, implementation, Test environment developmet etc.

Apply directly to: jay...@hcl.com

--
Jayan Chhaya
Associate Manager - Talent Acquisition Group
HCL America, Inc.

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