Looking for Design Verification Engineer in San Francisco Bay Area

[Vamshi Krishna Akuthota]

Hi,

Greetings from IMR Soft,

I’m reaching you regarding job opportunity with one of our clients. Please find the below full job description and share with me if you have any relevant resources.

 

Job Title: DV Engineer

Location: San Francisco, CA.

Duration: Long Term

 

Only GC/USC

 

Job Description

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities

• Develop and maintain UVM-based verification environments
• Create test plans, testcases, and coverage models
• Perform functional verification of RTL designs
• Debug RTL and testbench issues
• Drive coverage closure (functional + code)

Required Skills

• Strong hands-on with SystemVerilog and UVM
• Experience in block-level verification
• Good understanding of digital design fundamentals
• Experience with debug tools (Verdi, DVE, etc.)

Good to Have

• Exposure to low-power verification (UPF)

Experience with AMBA protocols (AXI/AHB/APB)

 

Thanks, 

 

Vamshi Krishna

 
732-592-2105
Vam...@imrsoft.com
www.imrsoft.com
IMR Soft LLC 4525 Rt 27 • Princeton, New Jersey 08540

                                                         

 

 

 

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