SSM IO4 debugging

[Todd Houg]

I figured out the problem with the IO4 having no serial data output from the COM8017 UARTS that I discussed in the Zoom call. I figured out that the Master Reset input to the UART was asserted. The IO4 buffers the S100 EXT_CLR* signal with a 74LS04 buffer to drive the UART Master Reset. I found that whenever the IO4 was plugged into the bus, EXT_CLR* was pulled low by the input of the LS04 buffer. After replacing the 74LS04, the reset was fixed and the UARTS started transmitting data.

Interestingly, the EXT_CLR* being asserted did not effect the 2SIOJP,  FDC+, CPU or front panel. It looks like EXT_CLR* is typically driven from the front panel, presumably on POC signal from the CPU card. How does front panel reset work with the 8800C? When does the panel assert PRESET* vs EXT_CLR? EXT_CLR only asserted on POC, PRESET asserted on POC or Reset sense switch?

Thanks,

   Todd

[Joseph Corda]

Great news Todd.. Thanks for sharing your findings / fix !

Joe

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[Mike Douglas]

Ext CLR is only asserted by the front panel operator. The idea was to use it as separate reset signal to peripherals like the PDP “reset external bus” sequence. Very few boards used the signal. I guess you’ve uncovered that the IO4 board was one of those few.

Mike D