7th Annual Heterogeneous Integration Roadmap Symposium
ASME K-16
Dear Colleagues
The organization team for the Multi-society Heterogeneous Integration Roadmap (HIR) would like to invite you to the “7th Annual Heterogeneous Integration Roadmap Symposium”.
Shown below is the two and half day program with invited speakers and their presentation titles. The conference will be held at the Samsung Electronics Campus 3655 N First Street San Jose California 95134.
On Wednesday afternoon, February 21st, there is a special session “Learning from the National Advanced Packaging Manufacturing Program (NAPMP)" with a Keynote presentation from Subramanian S. Iyer, NAPMP Director, followed by a Panel Session with invited distinguished Panelists. On February 22nd and 23rd the conference session in the morning (9:00 am to noon) will be presentations from the invited keynotes. In the afternoon the HIR Technical Working Groups will each give brief 2023-2024 update presentations during the afternoon sessions.
Registration is now open, at https://events.vtools.ieee.org/m/398899
There will be a nominal charge for registration. The registration fee goes towards expenses for box lunch, coffee during breaks and misc. expenses.
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Heterogeneous Integration Roadmap 7th Annual Conference
February 21, 22, 23, 2024
Samsung Electronics Campus
3655 N First Street, San Jose California, 95134
Wednesday February 21st , 2024
1:00 pm to 3:30 pm
Learning from the National Advanced Packaging
Manufacturing Program (NAPMP)
Keynote Presentation from Professor Subramanian S. Iyer, Director, National Advanced Packaging Manufacturing Program (NAPMP)
Panel / Fireside Chat with three guest panelists
Ajit Manocha - SEMI President
Nicky Lu – President ETRON
Tim Lee – IEEE USA President Elect & Boeing Fellow
&
Q&A from the floor
Moderators:
Ravi Mahajan & William Chen
Thursday February 22nd ,2024
9:00 am to 12:00 noon
Conference Opening Welcome
HIR Technology Focus and Future Vision
Keynote Speakers
Moonsoo Kang (Samsung)
Presentation Title; TBD
Alan Smith (AMD)
“AMD InstinctTM MI300 Series Modular Chiplet Package –
HPC and AI Accelerator for Exa-Class Systems”
Carl McCants (Darpa)
“Challenges and Opportunities in Manufacturing 3 dimentional
Heterogeneously Integrated (3DHI) Microsystem”
John Schreck & S.V. Sreenivasan (TIE UT Austin)
Presentation Title TBD
Lunch Break (75 minutes)
1:15 pm to 4:30 pm
HIR TWG Presentations
Wine Tasting
Friday February 23rd, 2024
Wei-Chung Lo/ Shih-Chieh Chang (EOSL-ITRI, Taiwan)
Presentation title (TBD)
Bob Wisniewski (Samsung)
“The Importance of Tight Coupling for Performance and Productivity”
Josh Fryman (Intel)
“Future architecture demands for more aggressive packaging”
Erik Jung/ Albert Heuberger (Fraunhofer Germany)
"Advanced Heterogenous Integration as a core activity
in the European ChipsJU Initiative"
Lunch Break (75 minutes)
1:15 pm to 4:30 pm
HIR TWG Presentations
HIR Town Hall