Assignment 4

1 view
Skip to first unread message

Kamal Kishor Pal

unread,
Mar 29, 2012, 12:53:43 PM3/29/12
to 2012eep3...@googlegroups.com
Hii,
If any group is stuck up in interfacing different VHDL files then you can implement everything in single VHDL file. This will simplify your design and you wont have to portmap.

Complete your assignment 4 asap so that you can devote more time for Lab Project!!  

--
Regards,
Kamal Kishor U.Pal


Reply all
Reply to author
Forward
0 new messages