Project 3: Always statements in top module?

[Matthew Beckler]

Hello 18340 students,

One of your classmates wrote in with a good question about project 3:

> Do we need to change the always block for the top module of the FPU?
> This is the part which controls the external registers of the FPU.
>
> Specifically this block:
>
> // Surrounding Registers to Clock the Design
> always @ (posedge clk) begin
> A <= A_reg;
> B <= B_reg;
> Y_reg <= Y;
> SEL = SEL_reg;
> Valid <= 1'b1;
> end
>
> Is this use of the always block permitted, or should we use the flip
> flop module in gatelib.v instead?

This always block will be permitted in your final design. It would be
uninteresting and tedious to convert such common notation to use the DFF
module from our gatelib.v file. Please let us know if you have any questions

-Matthew Beckler
18340 Systems Staff