Re: testbench_node_var_N
0 views
Skip to first unread message
Shawn Blanton
Apr 18, 2013, 8:54:57 AM4/18/13
to 18340...@googlegroups.com, 18340-stu...@googlegroups.com
fyi
On 4/17/2013 9:37 PM, Matthew Beckler wrote:
> The testbench samples on the rising edge of the clock because that is
> how 99% of all flip flops are designed, and is the generally-assumed
> behavior of a flip flop element. If you have a convincing argument as
> to how and why we should change this, please let us know and we will
> seriously consider it.
>
> Thanks much,
>
> Matthew Beckler
> 18340 System Staff
>
> On 04/17/2013 02:08 PM, ericbr...@cmu.edu wrote:
>> Why does the testbench sample valid_output on the rising edge of the
>> clock? Shouldn't it sample on the falling edge of the clock because
>> valid_output is modified on the rising edge of the clock?
>>
>> Thanks,
>> Eric
>>
>
On 4/17/2013 9:37 PM, Matthew Beckler wrote:
> The testbench samples on the rising edge of the clock because that is
> how 99% of all flip flops are designed, and is the generally-assumed
> behavior of a flip flop element. If you have a convincing argument as
> to how and why we should change this, please let us know and we will
> seriously consider it.
>
> Thanks much,
>
> Matthew Beckler
> 18340 System Staff
>
> On 04/17/2013 02:08 PM, ericbr...@cmu.edu wrote:
>> Why does the testbench sample valid_output on the rising edge of the
>> clock? Shouldn't it sample on the falling edge of the clock because
>> valid_output is modified on the rising edge of the clock?
>>
>> Thanks,
>> Eric
>>
>
Reply all
Reply to author
Forward
0 new messages