Generate Statements

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Mark Williams

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Apr 30, 2013, 12:30:10 PM4/30/13

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Hello 340 Staff,

I've already turned my LDPC code that compiled in vsim and ran as expected. I was also able to run DC compiler on it and everything processed and ran correctly, but I did use generate statements. Basically without them I'm going to have to copy paste everything 32 times and wire them together not really effecting the design of the circuit but basically increasing the chance that there I make a mistake. The design is going to be any different, but it will be significantly harder to read and understand. So should I just go and unravel the loop? or just leave it as it is.