Re: S13-Digital Computation: Project 4 - Generate statements not allowed

[John Greth]

Hey guys,

I just wanted to express my concerns about this change. I have had problems with generate statements in the past and have decided not to use them for this project. However, I know that several people have used them extensively and are done or almost done with the project. While I think that the reasons given are valid, I think that it is unfair to those people to make this change 3 days before it is due. Please consider amending this change!

Thanks!

John

On Apr 30, 2013, at 8:03 AM, mbec...@cmu.edu wrote:

 Hello everyone,

After receiving a question about the use of generate statements for Project 4, we have decided to not allow them for this project. Generate statements are a sort of meta-programming you can do in Verilog, to "lay down" gates or modules programatically. This can be useful when a module you design must consist of many copies of the same module with different port connections, such as the FA modules in a larger adder. However, the use of generate statements has several significant drawbacks, leading to us not allowing you to use them in Project 4:

1. The use of generate statements causes students to think flat, instead of hierarchically. We want you all to learn how to manage complex designs of medium-to-large size, and generate statements tend to encourage students to make flat designs. For the FA example above, consider making and using 4-bit adder sub-blocks to build your larger-width adder, instead of using dozens of FA modules directly. This will save you lots of debugging and verification time.
2. Compiler support for generate statements is not as reliable as you would hope for, and we have spent many hours this semester helping students with debugging their generate statements, due to compiler errors/warnings and odd behavior.