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Re: [beagleboard] Re: 2.6.26rc bootlog


Dirk May 15, 2008 11:18 AM
Posted in group: BeagleBoard
Laurent Desnogues wrote:
> On 5/15/08, Dirk Behme <dirk....@googlemail.com> wrote:
>
>>laurent....@gmail.com wrote:
>>
>>
>>>>CPU0: D VIPT write-through cache
>>>>CPU0: cache: 768 bytes, associativity 1, 8 byte lines, 64 sets
>>>>
>>>
>>>That's certainly wrong.  It seems the kernel fails to correctly
>>>detect ARMv7 cache properties.
>>>
>>
>> All: Sounds like this is something we have to discuss on arm kernel list
>>with RMK & Catalin? Shall I start a thread?
>
> Yes please, there is some code missing in kernel/setup.c to
> get this right.  This is only cosmetics, but it's good to have
> things properly detected and printed :-)

Short look into the details about this:

In arch/arm/kernel/setup.c there is:

if (CACHE_S(info)) {
   dump_cache("I cache", cpu, CACHE_ISIZE(info));
   dump_cache("D cache", cpu, CACHE_DSIZE(info));
} else {
    dump_cache("cache", cpu, CACHE_ISIZE(info));
}

Looks like on Beagle the else path is executed. With "info" containing

mrc        p15, 0, Rd, c0, c0, 1

this is because CACHE_S is defined as

#define CACHE_S(x)        ((x) & (1 << 24))

Looking to e.g. ARM926

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0198d/I1039291.html

this correct, as the S bit

"Specifies if the cache is a unified cache (S=0), or separate ICache
and DCache (S=1)"

But it seems that at Cortex-A8 p15, 0, Rd, c0, c0, 1 has completely
different meaning:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344e/Babgfegb.html

Dirk