wi...@ix.netcom.com(William H. Ivey) wrote: >In <4uo05b$e...@kannews.ca.newbridge.com> Paul DeMone ><pde...@tundra.com> writes: >> >> Maybe simple, but how was the 6502 efficient? IMHO the Z80 and >> 6809 were much nicer 8 bit micros to program. The only thing I >> liked about the 6502 was the binary/BCD ALU mode bit to avoid >> the need for DAA instructions. > >The average cycles-per-instruction on the 6502 was about 2 (thanks to >some basic pipelining). The Intel and Zilog chips required a lot more >cycles for even basic instructions. When I moved from a 4Mhs z80 to a
I think your CPI value for the 6502 is far too optimistic. IIRC the fastest 6502 instructions (immediate to accum) ran in 2 clocks, the others piled on cycles in a hurry. Regardless, it is not a meaningful comparison since the Z80 spread its memory access over 3 clocks (4 ?) while the 6502 required an entire memory access to take place in a single clock period to avoid wait states. Consider the effect of adding a single wait state to memory bandwidth of a Z80 vs a 6502. The 6502 prefetch was a nice touch though.
Cycle count based efficiency comparisons between the 6502 and Z80 are invalid even for internal processing. The Z80 had a 4 bit ALU that was cycled twice for 8 bit operations. On the average Z80, instructions took more cycles but much higher Z80 clock rates were achievable in comparable processes. This is similar to comparing an Alpha 21164A to a PowerPC 604e or P6 on the basis of average CPI but not considering differences in clock rate (the flip side of this - clock rate based comparisons ignoring differences in microarchitecture are equally invalid).
>1Mhz Apple IIe I was shocked at the speed improvment possible with a >bit of careful programming. (Even now, the 6502 beats out several other >processors - some of which struggle along with 11 cycles per >instruction.)
With a 4 MHz Z80, 11 clocks is faster than 3 clocks on a 1 MHz 6502; and a lot of 6502 instructions take longer than 3 clocks.
IMHO, If you got a speed improvement moving from a 4 MHz Z80 to a 1 MHz 6502 (assuming both platforms had no wait states) then the original code sure didn't exploit the full capabilities of the Z80 instructions and registers (or were running pretty atypical code).
My experience with both was that if you thoughtfully used all your registers and coded with an eye on the cycle counts you could make the Z80 really fly. OTOH, 6502 optimization tended to be limited to clever page zero management. The manipulation of 16 bit data and pointers was in particular a lot nicer and more efficient on the Z80 than the 6502.
> >> The 6502 architecture had nothing to do with RISC philosophy. If >> anything, the 6502 was a RTCC or Reduced Transistor Count CISC. >> The 6502 was register poor, had a multitude of addressing modes, >> and was a lousy compiler target; quite opposite characteristics >> from RISC CPUs. > > True, the 6502 had only three useful registers, but it had 256 >pseudo registers available externally for only a 1cycle penalty. Not
Look at it from the on-chip perspective. The internal logic decides in clock period 1 that it needs data from a page zero "register" so it sets up for an access in clock period 2 by forming the effective address. The address is driven out at the beginning of clock period 2 and, assuming no wait states, the data is clocked in at the end of clock period 2. It is then available for processing in clock period 3.
In reality your pseudo registers have a 1.5 - 2.0 clock period access time (vs < 0.5 for true register access) although some overlap is possible on chained or sequential accesses. On a Z80 the disparity is even greater given the multicycle memory access. Also, the use of Z80 register pairs (BC, DE, HL) or index registers gave quick access to any location in the 64K address space; the 6502 would burn two accesses just to fetch the effective address from page zero. Finally, the Z80 had a full 16 bit stack pointer which simplified stack management.
>much by today's cache standards, but impressive in it's time. That, and >a built in oscilator circuit made it a designer's dream. (The 65816 is
And the Z80 had a built-in refresh counter for DRAM support. These extras are nice but hardly relevent in comparing chip performance or "efficiency" of micro architectures.
>even more fun, 16 bit registers, and 24 bit addresses for many >operations. Let's you do a LOT in only 64K of code - the voice of >expereince speaks :-) -Wm
Yes, I remember when 64KB was but a hopeless, unaffordable dream ("who could possibly afford to populate all 64K ?" - it reminds me of current criticisms of 64 bit machines). When 16 KB was a high end machine it seemed like you could run a city with 64KB.
Now many CPUs have 64 KB or more of on-chip cache (21164, 604e, R5K, R10K, PA-7300LC) and Mitsubishi has put a 32 bit RISC CPU and 2 MB of DRAM on a single chip (M32R/D)!
BTW, comparing the pros and cons of the Z80 vs the 6502 must seem pretty distant to the kids debating Pentium vs 6x86 for running 3D games :-)
All opinions strictly my own.
-- Paul W. DeMone The 801 experiment SPARCed an ARMs race to put Kanata, Ontario more PRECISION and POWER into architectures with pde...@tundra.com MIPSed results but ALPHA's well that ends well.
Satan's CPU? The P666 of course - check out Appendix H(ell) under NDA