UNC-CH CS Colloquium - Barton Sano - April 18, 1994
Donna Boggs
The University of North Carolina at Chapel Hill
COLLOQUIUM
Barton Sano
University of Southern California
Monday, April 18, 1994
10:00 a.m.
011 Classroom, Sitterson Hall
Refreshments will be served afterwards in the lower lobby
The 16-Fold Way: A Microparallel Taxonomy
This talk presents a novel microparallel taxonomy for machines with
multiple-instruction processing capabilities including VLIW, superscalar,
and decoupled machines. The taxonomy is based upon the static or dynamic
behavior of four abstract, operational stages that an instruction passes
through. These stages are fetch, decode, execute, and retire. This two
valued, four variable taxonomy results in sixteen ways that a processor's
microarchitecture can be specified. We categorize different machine
instances that are either actual implementations or proposed systems within
the taxonomy framework. Two new processor microarchitectures are presented
which provide additional features.
The potential performance of these processors are determined by a related
study which measures the ideal instruction-level parallelism for different
classifications. A promising processor organization called the "Multi-Spec"
is proposed as an instance of a general classification of multiple-control
flow processors with speculative execution capabilities. It is shown that
advanced CMOS technology could support the instruction bandwidth requirements
of the Multi-Spec.
Biosketch:
Barton Sano earned his BS in Computer Science from Cal. Berkeley,
his MS from USC, and expects his to finish his PhD this summer also
from USC. Barton's research and teaching interests include high-performance
computer architectures, VLSI system design, and symbolic processing. To this
end he has worked for a startup company which developed a symbolic coprocessor
for the SUN workstations. He also managed a design group, while at Cal.
Berkeley, which produced the VLSI-BAM, a 30 MHz CMOS RISC processor
achieving the highest reported Prolog performance at the time. He is
currently working on a 200 MHz superpipelined processor fabricated in
1.0um CMOS and is using this design experience to model the cost and
performance of microparallel processors, which is the topic his talk.
Host: John Poulton, 962-1743, e-mail pou...@cs.unc.edu