How ICs are made - the inside track...

[Nick]

A friend who is one of only a handful of lens designers for modern FABs (IC fabrication plants) a while ago wrote up the following - It explains some of the enormous complexity of IC photo-lithography - amazing stuff really... read and enjoy...

Nick

ICs are produced by depositing layers of material onto a silicon substrate, coating it with photo-resist, exposing the resist in a thing like a glorified slide projector, then developing it and etching away the original material (or implanting the whole thing in an ion implanter to dope the exposed area of silicon). Anyone who's had a go at making their own PCBs will understand the principal. It's the detail that's astonishing. First of all, as mentioned above, the smallest feature printed on the silicon can be as little as 40nm across. Lets get that in perspective. A human hair (the universal indicator of smallness in the same way that football pitches and double-decker buses are the universal bigness indicators) is about 80 microns in diameter, so one micron is one 80th of a hair. 40nm is four hundredths of one micron, so about 1/2000th of a hair. Features that small have to be printed with perfect definition across a field up to 30mm square. Since the silicon substrate (or wafer, as they're known) we're talking about is up to 300mm in diameter, a grid of exposures is made, with the wafer being moved on a stage under the lens from step to step (hence stepper) until the whole wafer is covered. 

That's the easy bit. 

Chips are made up from up to thirty layers of material, each one with its own pattern, which of course has to be aligned to the one below to an accuracy of about .01 microns. Think about that. The wafer is 12" in diameter, and is sitting on a stage made of quartz about 15mm thick. That in turn sits on piezo feet that keep the image in focus (depth of field is around 1 micron). This whole assembly weighs about thirty kilos, and has to be aligned under the lens, focussed, exposed, then moved to the next image, aligned again to .01 micron, focussed and exposed in a cycle that takes around one second. To achieve this, the stage sits on an air cushion on top of a lump of granite that weighs around half a ton, and is driven in x and y by a couple of hefty great linear motors, position being measured by laser interferometers. This one-second cycle covers a wafer in about thirty five shots, so a wafer goes through in about 45 seconds, hour after hour, day after day. Astonishing.

The current production lenses use 193nm deep UV . They consist of a lens about 1.5m long made up of 30-35 elements made from Calcium Fluoride and Fused Silica , up to 220mm diameter. Essentially it's like a giant microscope objective working in reverse, taking mask designs at 5x final scale and reducing them onto an active chip area of about 30x30mm.

Originally , lenses at 193nm were operating at NA of 0.5 ( = F/1 ) in air, and diffraction-limited. That gave about 90-100nm linewidth, I think. Since then, they have pushed the designs to an NA of over 0.9 in air, then with water immersion between the lens and wafer, to an effective NA of 1.3 - which is how the 40-50nm linewidths have been achieved. 

The lens element surfaces have to be finished to an regularity of about 1/100th of a wave of light or better, in the visible. This requires conventional polishing followed by cycles of measurement and ion-beam-figuring ( I believe ) to finish.

The lens elements are mounted into Invar ( ~zero expansion) cells and assembled as a stack, one lens at a time, using optical monitoring of the lens to get it centred. The Invar cells are diamond-machined to about 0.5 micron parallelism. 

These lenses produce by far the most 'information' in one shot, of any optical systems made in any field. If you wanted to capture the available detail from this lens using a digital sensor, you would need to use about 430 Giga-pixels - I know as I calculated this recently for interest, after seeing an impressive 2G-pix image assembled from shots above Everest base camp. 

Alternatively, consider that if the chip was enlarged to 400x400m , the line structures would be at the 0.5mm level . 

Very few people understand the extraordinary technology that goes into the common processor chips that are in their computers

[gregebert]

Thanks for posting. To put things into perspective, I was working on a 40nm project (the above posting mentions 40-40nm process technology) 10 years ago, and we actually switched it to 32nm. And that was also 10 years ago. A lot has changed since then.

You wouldn't believe the things we did to get 14nm chips working in high-volume manufacturing.

I'm currently managing a 10nm project, and it's definitely much more challenging.

[Dekatron42]

I just finished reading the article "The Molten Tin Solution" by Rachel Courtland in IEE Spectrum which explains some of the EUV chip-printing technology so this description was a nice view from another side of the complexities of producing ic's, especially as they talked about the problem making mirrors and lenses that could reflect the wavelengths used in the process.

Unfortunately the article is behind a paywall, but for those interested you can probably find it in a library.

[Roddy Scott]

I started in PCB manufacture with 'punch and crunch' double sided PCBs and ended up maintaining 24 layer 4 thou track and gap equipment which was cutting edge at the time. Spent 11 1/2 years in CMP going from 64nm on 200mm wafers to 14nm on 300mm wafers. Now 7nm on 400mm wafers are on the horizon.

I hear your pain!

[threeneurons]

In 1985, shortly after, I got out of school, they just broke the 1 micron barrier. I think wafers were ~5" (~130mm).

From the few people I've known, that were in the semi business, they change "mask sets" for parts routinely, for an existing part. This is due to keeping up to the current process (shrinking resolution, and growing wafer size, etc). So a 555 made today is not the same 555 made 30 years go, Probably not the same one made 2 years ago.

[gregebert]

1985 was my 'golden year' as well. Started work at TRW doing 2 micron CMOS design for the Milstar program. Several of those birds are still in orbit, and with several of the ICs I worked on. That old technology sure is rugged.

At some point, the process technology:

• Doesn't result in further die-area reduction due to limiting factors such as finite bonding-pad (ie, minimum) size
  
• Is incapable of running at higher voltages (you cant put 15 volts on a 10nm transistor)
• Becomes too expensive and is no longer offset by higher die-per-wafer

I remember we had special thick-oxide transistors to handle 3.3V on 0.13 micron (130nm); it could not handle 5V. I'm sure that legacy devices like the 741, 555, etc require older process technologies just for supply-voltage reasons. I just checked MOSIS (they do small-run IC designs), and they use ON-SEMI for 0.7micron fabrication. That was state-of-the-art process technology 25 years ago so it still must be used for current production of legacy IC's.

It's hard to wrap your head around all of the IC process technology. Smaller generally means faster and more power-efficient, but it also costs more and takes longer to produce.  I believe the 741 will celebrate it's 50th birthday next year, and they're still in production.

[Roddy Scott]

There is a scaled up exploded model of a Pentium that was a 1M cube where I worked.

 

When you think about it at that time, 1993, it contained 3.1 million transistors, 8kb cache, 8kb data and ran at a maximium of 66MHz and was built on 0.8µm technology .

Compare that with what is now on the market, Skylake, 1,750 million transistors, running at 4GHz, and with 14nm technology.

Moore's Law predicted that the number of transistors in a processor would double every year, this is only achievable now due to 3D transistor architecture and the processes behind them. Processor chips may have gotten a little bit bigger but not by much but could you imagine the size of a computer based on the ENIAC technology and the power requirements? The original consumed 150KW and weighed about 30 tons, a modern day version would need its own power station and would take up a football stadium, the heat generated by it could warm a small country, mind you, think of all those counters that would be available if they scrapped it!

 

[Charles MacDonald]

On 17-01-24 03:14 AM, Roddy Scott wrote:
Processor chips
> may have gotten a little bit bigger but not by much but could you
> imagine the size of a computer based on the ENIAC

> <https://en.wikipedia.org/wiki/ENIAC> technology and the power

> requirements? The original consumed 150KW and weighed about 30 tons, a
> modern day version would need its own power station and would take up a
> football stadium

Ah but you are forgetting as Admiral Hopper liked to point out, the size
of a nanosecond. A football stadium sized computer could not get out of
it's own way.

--
Charles MacDonald Stittsville Ontario
cm...@zeusprune.ca Just Beyond the Fringe
No Microsoft Products were used in sending this e-mail.

[chuck richards]

Yes, that is correct! Because electricity travels
through a wire at the approximate speed of 1 nanosecond per foot!

Chuck

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[jb-electronics]

What I find particulary amusing is that the drift velocity of the actual
electrons is of the order of a cm/s if I remember correctly. Jens

[chuck richards]

Yep, there's that part of it to consider as a portion
of the total overall result.

But, check it out, do the math. The speed of light
is roughly one nanosecond per foot.

Yes, yes, electricity "flows" through a wire some tiny bit
slower than that, but the above approximation gets it well
within decent enough accuracy to aid a person in "seeing" what
is happening.

One time at Verizon we had a timing issue due to combining both 50
foot and 100 foot clock cables to different processor complexes
in a GTD-5 electronic telephone exchange. That clock runs at 12.352
mHz.

I pointed out that the clock pulses were arriving at the end of the
100 foot cable about 50 nS later than those pulses arriving at the
end of the 50 foot cable. That indeed was the problem.

We swapped out the 50 footers and made them all 100 footers, and
that cleared the trouble.

>https://groups.google.com/d/msgid/neonixie-l/69f561eb-f570-41d0-6959-
>6993691b263b%40jb-electronics.de.

[Instrument Resources of America]

I had a very similar issue here in my lab recently while checking out an
HP X-Y display. I was feeding both x and y the same signal in order to
check out the phase spec between both ch. at 20 MHZ. Unfortunately idiot
here had used two different length cables to feed x and Y, and then sat
there trying to figure out why it would NOT meet spec. It finally dawned
on me. Two equal length cables solved the issue. Ira.

[Instrument Resources of America]

P.S. getting old is the pits!!!

[robin bussell]

Hence the messy appearance of the internal wiring on a cray
supercomputer, lots of lines had to be kept the same length to keep the
timeing right:

http://www.digibarn.com/collections/systems/crays/cray1/portrait/DSC08221.JPG

(sorry for transistorised OT :) )

Cheers,
Robin.

[JohnK]

Many years ago [50] in school physics we were told 27 feet per second for
'electrons' in wire and to treat "data/information" transfer like a long
tube full of ping-pong balls where you push one in at this end and one falls
out at the other.

John K

> https://groups.google.com/d/msgid/neonixie-l/69f561eb-f570-41d0-6959-6993691b263b%40jb-electronics.de.

[jb-electronics]

27ft/s seems high, see here:
https://en.wikipedia.org/wiki/Drift_velocity#Numerical_example

Jens

[JohnK]

Yeah, it probably is wrong. That was why I said it WAS 50 years ago. Maybe I
misremembered the figure too. They did describe the experiment that provided
the figure but I have zero recollection of that for some reason.
Maybe I misremembered more too. Interesting that the 3 inches per hour
would be close to 2.7 inches per hour. I still have a lot of the old school
books - I can picture the book involved as a softcover A4 on its edge
variety. One that was written by a group of physics teachers specifically
for the curriculum; very easy for there to be errors in it - they got Static
and Dynamic tube/valve curves confused.

Point is though, 'electrons' travel slowly, the effect travels quickly. Yes?

jk

> https://groups.google.com/d/msgid/neonixie-l/b5b30139-7838-51fd-95f3-528c8257328b%40jb-electronics.de.

[chuck richards]

Yes, it's sort of the same idea as when a long freight train
grinds to a stop at less than 1 mile per hour and then you hear
the slack in all of the couplers going in, and that wave travels
the length of the train at around 30 mph, even though the train
is nearly motionless.

The secret to it seems to be that each electron does not have to
travel very far until "bumping" its neighbor.

>https://groups.google.com/d/msgid/neonixie-l/38A56FAD54B44DBEA3810C96
>10A47F29%40compunet4f9da9.

[jb-electronics]

Yeah exactly. I just think it is interesting that even though electric
signals can travel ridiculously fast, one is stuck with one's personal
electrons for quite some time until they bid farewell. Jens