How to simulate a dut including parameters overall?

[Sand Glass]

First Given a case:

test.v 

module test( 

a,b 

); 

parameter AA = 1; 

input a; 

output b; 

assign b = AA==1'b1 ? a : 0; 

endmodule 

tb.v 

module tb(); 

parameter PAR_A = 0; 

//int width; 

//scanf(width); 

//if(width == 10)PAR_A=0; 

//else if(width == 20)PAR_A=1; 

test #(.AA(PAR_A)) test_dut( 

  .a(1'b1), 

  .b() 

); 

endmodule 

When I simulating the test.v, I need to simulate variable cases, like 

PAR_A = 1, PAR_A=0, PAR_A = other value. 

How can I do it automatically(like the upper commented code block)? 

The environment(modelsim SE) support systemveilog, but tb.v cannot be changed to tb.sv.