Does the L2 cache matter in Minix 3 ?

[Channing Ma]

Hi, everyone.

As we know Minix can support BeagleBoard XM and BeagleBone which contains a Cortex-A8 processor, where the L2 Cache is
implemented inside the processor. Now I am going to run Minix on the Zynq-7000 which contains a Cortex-A9
processor, where the L2 cache is external to the processor.

In the Minix source, kernel/arch/earm/pg_utils.c: line 234: vm_enable_paging() : enable the Cortex-A8 L2 cache by writing
Auxiliary Control Register. If running the Minix on the Cortex-A9, is this operation essential? or optional? if it must be done,
how to do that?

Related hardware specification:
" 7.19.1 Level 2 cache maintenance
               we saw earlier how the programmer may need the ability to clean and/or invalidate some or all
               of a cache. This can be done by writing to memory-mapped registers within the L2 cache controller
               in the case where the cache is external to the processor,(as with the Cortex-A5 and Cortex-A9 processors),
               or through CP15 (where the level 2 cache is implemented inside the processor(as with the Cortex-A8 processor).
               Where such operations are performed by having the processor perform memory-mapped writes,
               the processors needs a way of determining when the operation is complete. It does this by polling
               a further memory-mapped register within the L2 cache."

I wonder if it does matter to initialize the L2 cache in Minix boot time if it runs on the Cortex-A9. Because in my present
situation, kernel is booted on the Zynq-7000 but VM gets the pagefault lethal exception. The system isn't going on.