no icache loads ?

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Erik Vanherck

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Mar 14, 2016, 12:04:52 PM3/14/16
to mechanical-sympathy
I'm just toying around with perf on a recent Hashwell Xeon system and when having it report some counters I noticed that for our own java stacks its reporting 0 icache loads ? isn't this extremely fishy ? Would this be triggered by the JVM code generation (it should have long warmed up already) or is the code base simply too large (it's a huge stack).

 Performance counter stats for process id '12201':


    5601976.588516      task-clock (msec)         #   11.785 CPUs utilized          

14,373,016,272,513      cycles                    #    2.566 GHz                     [44.45%]

12,426,542,508,899      instructions              #    0.86  insns per cycle         [55.57%]

    80,682,990,813      LLC-loads                 #   14.403 M/sec                   [55.58%]

    16,502,526,162      LLC-load-misses           #   20.45% of all LL-cache hits    [55.14%]

   198,532,385,039      cache-references          #   35.440 M/sec                   [53.66%]

    28,705,183,593      cache-misses              #   14.459 % of all cache refs     [53.21%]

 3,805,681,596,805      L1-dcache-loads           #  679.346 M/sec                   [45.69%]

   214,992,359,495      L1-dcache-load-misses     #    5.65% of all L1-dcache hits   [45.65%]

                 0      L1-icache-loads           #    0.000 K/sec                  

   134,328,141,793      L1-icache-load-misses     #   23.979 M/sec                   [46.75%]


     475.365301765 seconds time elapsed



Matt Godbolt

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Mar 15, 2016, 8:48:30 AM3/15/16
to mechanical-sympathy
Seems like the icache-load counter isn't being set up right (or has changed in a way that perf doesn't know about). Obviously there's things loading into icache (else the "icache-load-misses" would be zero too..)

From a cursory glance through Intel manuals 3B part 2 it seems the counter has gone. Event 80h mask 02h is "icache misses", but there's no "hits" counter. If one scrolls back to Core i7, there are "l1i.misses" (80h:02h) and also "l1i.hits" (80h:01h), as well as the logical combination "l1i.reads" (80h:03h).

Intel aren't always good at documenting these things, so it's feasible there's a counter somewhere still that counts hits and accesses. Perhaps even on Sandy et al, the 80h:01h counter existed (undocumented). But it seems to be gone now.

--matt

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