[PATCH v2 1/5] dmaengine: mv_xor: make the code 64 bits compliant

[Gregory CLEMENT]

Fix two warnings which appear when building for 64 bits target.

Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>
---
drivers/dma/mv_xor.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 3922a5d56806..a6ec82776cbc 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -477,7 +477,7 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);

dev_dbg(mv_chan_to_devp(mv_chan),
- "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
+ "%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
__func__, src_cnt, len, &dest, flags);

sw_desc = mv_chan_alloc_slot(mv_chan);
@@ -1220,7 +1220,7 @@ static int mv_xor_probe(struct platform_device *pdev)
struct mv_xor_chan *chan;
dma_cap_mask_t cap_mask;
int irq;
- op_in_desc = (int)of_id->data;
+ op_in_desc = (uintptr_t)of_id->data;

if (i >= max_channels)
continue;
--
2.5.0

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada 3700 SoC comprise one dual-channel XOR engine and this
patch adds its according representation.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>

Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>
---

arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index ba9df7ff2a72..932783d82ea9 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -112,6 +112,19 @@
status = "disabled";
};

+ xor@60900 {
+ compatible = "marvell,armada-3700-xor";
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
+
+ xor10 {
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ xor11 {
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
sata@e0000 {
compatible = "marvell,armada-3700-ahci";
reg = <0xe0000 0x2000>;
--
2.5.0

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada 3700 SoC comprise a single XOR engine compliant with the ones used
in older Marvell SoC's like Armada XP or 38x. The only thing that needs
modification is the Mbus configuration, which has to be done on two
levels: global and in device. The first one is inherited from the
bootlader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed.

Patch "dmaengine: mv_xor: optimize performance by using a subset
of the XOR channels" introduced limitation for using XOR engines and
channels vs number of available CPU's. Those contstraints do not however
fit Armada 3700 architecture with two possible CPU's and single,
dual-channel engine. Hence in this commit an adjustment for setting
maximum available channels is added.

This patch enables XOR access to DRAM by opening default window to 4GB
space with specific attribute.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>

Acked-by: Rob Herring <ro...@kernel.org>
---
Documentation/devicetree/bindings/dma/mv-xor.txt | 5 ++-
drivers/dma/mv_xor.c | 56 +++++++++++++++++++++---
2 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/mv-xor.txt b/Documentation/devicetree/bindings/dma/mv-xor.txt
index 276ef815ef32..c075f5988135 100644
--- a/Documentation/devicetree/bindings/dma/mv-xor.txt
+++ b/Documentation/devicetree/bindings/dma/mv-xor.txt
@@ -1,7 +1,10 @@
* Marvell XOR engines

Required properties:
-- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"
+- compatible: Should be one of the following:
+ - "marvell,orion-xor"
+ - "marvell,armada-380-xor"
+ - "marvell,armada-3700-xor".
- reg: Should contain registers location and length (two sets)
the first set is the low registers, the second set the high
registers for the XOR engine.
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 6d012a56b97b..25d1dadcddd1 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -34,6 +34,7 @@
enum mv_xor_type {
XOR_ORION,
XOR_ARMADA_38X,
+ XOR_ARMADA_37XX,
};

enum mv_xor_mode {
@@ -1093,6 +1094,33 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
}

+static void
+mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
+{
+ void __iomem *base = xordev->xor_high_base;
+ u32 win_enable = 0;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ writel(0, base + WINDOW_BASE(i));
+ writel(0, base + WINDOW_SIZE(i));
+ if (i < 4)
+ writel(0, base + WINDOW_REMAP_HIGH(i));
+ }
+ /*
+ * For Armada3700 open default 4GB Mbus window. The dram
+ * related configuration are done at AXIS level.
+ */
+ writel(0xffff0000, base + WINDOW_SIZE(0));
+ win_enable |= 1;
+ win_enable |= 3 << 16;
+
+ writel(win_enable, base + WINDOW_BAR_ENABLE(0));
+ writel(win_enable, base + WINDOW_BAR_ENABLE(1));
+ writel(0, base + WINDOW_OVERRIDE_CTRL(0));
+ writel(0, base + WINDOW_OVERRIDE_CTRL(1));
+}
+
/*
* Since this XOR driver is basically used only for RAID5, we don't
* need to care about synchronizing ->suspend with DMA activity,
@@ -1137,6 +1165,11 @@ static int mv_xor_resume(struct platform_device *dev)
XOR_INTR_MASK(mv_chan));
}

+ if (xordev->xor_type == XOR_ARMADA_37XX) {
+ mv_xor_conf_mbus_windows_a3700(xordev);
+ return 0;
+ }
+
dram = mv_mbus_dram_info();
if (dram)
mv_xor_conf_mbus_windows(xordev, dram);
@@ -1147,6 +1180,7 @@ static int mv_xor_resume(struct platform_device *dev)
static const struct of_device_id mv_xor_dt_ids[] = {
{ .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
{ .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
+ { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
{},
};

@@ -1204,9 +1238,13 @@ static int mv_xor_probe(struct platform_device *pdev)
/*
* (Re-)program MBUS remapping windows if we are asked to.
*/
- dram = mv_mbus_dram_info();
- if (dram)
- mv_xor_conf_mbus_windows(xordev, dram);
+ if (xordev->xor_type == XOR_ARMADA_37XX) {
+ mv_xor_conf_mbus_windows_a3700(xordev);
+ } else {
+ dram = mv_mbus_dram_info();
+ if (dram)
+ mv_xor_conf_mbus_windows(xordev, dram);
+ }

/* Not all platforms can gate the clock, so it is not
* an error if the clock does not exists.
@@ -1220,12 +1258,16 @@ static int mv_xor_probe(struct platform_device *pdev)
* order for async_tx to perform well. So we limit the number
* of engines and channels so that we take into account this
* constraint. Note that we also want to use channels from
- * separate engines when possible.
+ * separate engines when possible. For dual-CPU Armada 3700
+ * SoC with single XOR engine allow using its both channels.
*/
max_engines = num_present_cpus();
- max_channels = min_t(unsigned int,
- MV_XOR_MAX_CHANNELS,
- DIV_ROUND_UP(num_present_cpus(), 2));
+ if (xordev->xor_type == XOR_ARMADA_37XX)
+ max_channels = num_present_cpus();
+ else
+ max_channels = min_t(unsigned int,
+ MV_XOR_MAX_CHANNELS,
+ DIV_ROUND_UP(num_present_cpus(), 2));

if (mv_xor_engine_count >= max_engines)
return 0;
--
2.5.0

[Gregory CLEMENT]

Hi,

This series adds the support of the Marvell XOR engine to the Armada
3700 SoC. As this SoC is an ARM64 one, then the code has been fixed to
support the 64 bits platform.

The initialization for the Armada 3700 is different from the other
SoCs, so in order to support it, a new way of handling the different
family have been added.

Once the dmaengine part will be approved, I will apply the dts part
in the mvebu/dt64 tree.

In this second version I took into account the remarks from Rob
Herring about the patch related to the binding.

Thanks,

Gregory

Changelog:
v1 ->v2:
- Fix typo in commit log of patch 3
- Reformatting to 1 compatible string per line in
Documentation/devicetree/bindings/dma/mv-xor.txt
- Added Acked-by from Rob in patch 3

Gregory CLEMENT (3):
dmaengine: mv_xor: make the code 64 bits compliant
dmaengine: mv_xor: use SoC type instead of directly the operation mode
dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible
SoC

Marcin Wojtas (2):
dmaengine: mv_xor: add support for Armada 3700 SoC
arm64: dts: marvell: add XOR node for Armada 3700 SoC

Documentation/devicetree/bindings/dma/mv-xor.txt | 5 +-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 13 ++++
drivers/dma/Kconfig | 2 +-
drivers/dma/mv_xor.c | 98 +++++++++++++++++++-----
drivers/dma/mv_xor.h | 1 +
5 files changed, 97 insertions(+), 22 deletions(-)

--
2.5.0

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada 3700 SoC comprise one dual-channel XOR engine and this
patch adds its according representation.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>

[Gregory CLEMENT]

Hi,

This series adds the support of the Marvell XOR engine to the Armada
3700 SoC. As this SoC is an ARM64 one, then the code has been fixed to
support the 64 bits platform.

The initialization for the Armada 3700 is different from the other
SoCs, so in order to support it, a new way of handling the different
family have been added.

Once the dmaengine part will be approved, I will apply the dts part
in the mvebu/dt64 tree.

In this third series I took into account the remark from Jason Cooper
about adding the COMPILE_TEST dependency.

Thanks,

Gregory

Changelog:
v2 -> v3:
- Add COMPILE_TEST dependency

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada 3700 SoC comprise a single XOR engine compliant with the ones used
in older Marvell SoC's like Armada XP or 38x. The only thing that needs
modification is the Mbus configuration, which has to be done on two
levels: global and in device. The first one is inherited from the
bootlader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed.

Patch "dmaengine: mv_xor: optimize performance by using a subset
of the XOR channels" introduced limitation for using XOR engines and
channels vs number of available CPU's. Those contstraints do not however
fit Armada 3700 architecture with two possible CPU's and single,
dual-channel engine. Hence in this commit an adjustment for setting
maximum available channels is added.

This patch enables XOR access to DRAM by opening default window to 4GB
space with specific attribute.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>

[Gregory CLEMENT]

Currently the main difference between legacy XOR engine and newer one, is
the way the engine modes are setup (either in the descriptor or through
the controller registers). In order to be able to take into account new
generation of the XOR engine for the ARM64 SoC, we need to identify them
by type, and then depending to the type the engine setup will be
selected.

Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>
---

drivers/dma/mv_xor.c | 40 ++++++++++++++++++++++++++++------------
drivers/dma/mv_xor.h | 1 +
2 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index a6ec82776cbc..6d012a56b97b 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -31,6 +31,11 @@
#include "dmaengine.h"
#include "mv_xor.h"

+enum mv_xor_type {
+ XOR_ORION,
+ XOR_ARMADA_38X,
+};
+
enum mv_xor_mode {
XOR_MODE_IN_REG,
XOR_MODE_IN_DESC,
@@ -933,7 +938,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
static struct mv_xor_chan *
mv_xor_channel_add(struct mv_xor_device *xordev,
struct platform_device *pdev,
- int idx, dma_cap_mask_t cap_mask, int irq, int op_in_desc)
+ int idx, dma_cap_mask_t cap_mask, int irq)
{
int ret = 0;
struct mv_xor_chan *mv_chan;
@@ -945,7 +950,10 @@ mv_xor_channel_add(struct mv_xor_device *xordev,

mv_chan->idx = idx;
mv_chan->irq = irq;
- mv_chan->op_in_desc = op_in_desc;
+ if (xordev->xor_type == XOR_ORION)
+ mv_chan->op_in_desc = XOR_MODE_IN_REG;
+ else
+ mv_chan->op_in_desc = XOR_MODE_IN_DESC;

dma_dev = &mv_chan->dmadev;

@@ -1137,8 +1145,8 @@ static int mv_xor_resume(struct platform_device *dev)

}

static const struct of_device_id mv_xor_dt_ids[] = {

- { .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG },
- { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC },
+ { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
+ { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
{},
};

@@ -1152,7 +1160,6 @@ static int mv_xor_probe(struct platform_device *pdev)
struct resource *res;
unsigned int max_engines, max_channels;
int i, ret;
- int op_in_desc;

dev_notice(&pdev->dev, "Marvell shared XOR driver\n");

@@ -1180,6 +1187,20 @@ static int mv_xor_probe(struct platform_device *pdev)

platform_set_drvdata(pdev, xordev);

+
+ /*
+ * We need to know which type of XOR device we use before
+ * setting up. In non-dt case it can only be the legacy one.
+ */
+ xordev->xor_type = XOR_ORION;
+ if (pdev->dev.of_node) {
+ const struct of_device_id *of_id =
+ of_match_device(mv_xor_dt_ids,
+ &pdev->dev);
+
+ xordev->xor_type = (uintptr_t)of_id->data;
+ }
+

/*
* (Re-)program MBUS remapping windows if we are asked to.
*/

@@ -1212,15 +1233,11 @@ static int mv_xor_probe(struct platform_device *pdev)
if (pdev->dev.of_node) {
struct device_node *np;
int i = 0;
- const struct of_device_id *of_id =
- of_match_device(mv_xor_dt_ids,
- &pdev->dev);

for_each_child_of_node(pdev->dev.of_node, np) {

struct mv_xor_chan *chan;
dma_cap_mask_t cap_mask;
int irq;

- op_in_desc = (uintptr_t)of_id->data;

if (i >= max_channels)
continue;

@@ -1237,7 +1254,7 @@ static int mv_xor_probe(struct platform_device *pdev)
}

chan = mv_xor_channel_add(xordev, pdev, i,
- cap_mask, irq, op_in_desc);
+ cap_mask, irq);
if (IS_ERR(chan)) {
ret = PTR_ERR(chan);
irq_dispose_mapping(irq);
@@ -1266,8 +1283,7 @@ static int mv_xor_probe(struct platform_device *pdev)
}

chan = mv_xor_channel_add(xordev, pdev, i,
- cd->cap_mask, irq,
- XOR_MODE_IN_REG);
+ cd->cap_mask, irq);
if (IS_ERR(chan)) {
ret = PTR_ERR(chan);
goto err_channel_add;
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index c19fe30e5ae9..bf56e082e7cd 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -85,6 +85,7 @@ struct mv_xor_device {
void __iomem *xor_high_base;
struct clk *clk;
struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
+ int xor_type;
};

/**
--
2.5.0

[Gregory CLEMENT]

Fix two warnings which appear when building for 64 bits target.

Signed-off-by: Gregory CLEMENT <gregory...@free-electrons.com>
---

drivers/dma/mv_xor.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 3922a5d56806..a6ec82776cbc 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c

@@ -477,7 +477,7 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);

dev_dbg(mv_chan_to_devp(mv_chan),
- "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
+ "%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
__func__, src_cnt, len, &dest, flags);

sw_desc = mv_chan_alloc_slot(mv_chan);

@@ -1220,7 +1220,7 @@ static int mv_xor_probe(struct platform_device *pdev)

struct mv_xor_chan *chan;
dma_cap_mask_t cap_mask;
int irq;

- op_in_desc = (int)of_id->data;
+ op_in_desc = (uintptr_t)of_id->data;

if (i >= max_channels)
continue;

--
2.5.0

[Vinod Koul]

On Thu, Apr 14, 2016 at 06:53:38PM +0200, Gregory CLEMENT wrote:
> From: Marcin Wojtas <m...@semihalf.com>
>
> Armada 3700 SoC comprise one dual-channel XOR engine and this
> patch adds its according representation.

This need an ACK from ARM folks..

--
~Vinod

[Thomas Petazzoni]

Hello Vinod,

On Tue, 26 Apr 2016 09:05:36 +0530, Vinod Koul wrote:
> On Thu, Apr 14, 2016 at 06:53:38PM +0200, Gregory CLEMENT wrote:
> > From: Marcin Wojtas <m...@semihalf.com>
> >
> > Armada 3700 SoC comprise one dual-channel XOR engine and this
> > patch adds its according representation.
>
> This need an ACK from ARM folks..

Well, this patch has the SoB from Gregory Clement, who is one of the
maintainers of the ARM Marvell Armada platforms. And he should be the
one taking this patch in his tree (especially since a lot of others
Armada 3700 DT changes are going to be made).

So I guess that the intent is that you take patches 1 to 4, and patch 5
will be taken by Gregory.

Best regards,

Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[Vinod Koul]

On Thu, Apr 14, 2016 at 06:53:34PM +0200, Gregory CLEMENT wrote:
> Fix two warnings which appear when building for 64 bits target.

It is a good practice to post the warnings in log so that people know what
is being fixed

--
~Vinod

[Vinod Koul]

On Tue, Apr 26, 2016 at 09:28:11AM +0200, Thomas Petazzoni wrote:
> Hello Vinod,
>
> On Tue, 26 Apr 2016 09:05:36 +0530, Vinod Koul wrote:
> > On Thu, Apr 14, 2016 at 06:53:38PM +0200, Gregory CLEMENT wrote:
> > > From: Marcin Wojtas <m...@semihalf.com>
> > >
> > > Armada 3700 SoC comprise one dual-channel XOR engine and this
> > > patch adds its according representation.
> >
> > This need an ACK from ARM folks..
>
> Well, this patch has the SoB from Gregory Clement, who is one of the
> maintainers of the ARM Marvell Armada platforms. And he should be the
> one taking this patch in his tree (especially since a lot of others
> Armada 3700 DT changes are going to be made).
>
> So I guess that the intent is that you take patches 1 to 4, and patch 5
> will be taken by Gregory.

sounds good to me then

thanks
--
~Vinod

[Vinod Koul]

On Thu, Apr 14, 2016 at 06:53:36PM +0200, Gregory CLEMENT wrote:
> From: Marcin Wojtas <m...@semihalf.com>
>
> Armada 3700 SoC comprise a single XOR engine compliant with the ones used
> in older Marvell SoC's like Armada XP or 38x. The only thing that needs
> modification is the Mbus configuration, which has to be done on two
> levels: global and in device. The first one is inherited from the
> bootlader. The latter can be opened in a default way, leaving

s/bootlader/bootloader

> arbitration to the bus controller. Hence filled mbus_dram_target_info
> structure is not needed.
>
> Patch "dmaengine: mv_xor: optimize performance by using a subset
> of the XOR channels" introduced limitation for using XOR engines and
> channels vs number of available CPU's. Those contstraints do not however

s/contstraints/constraints

--
~Vinod