Re: [PATCH v1 0/8] ARM: sunxi: dram.c: Multiple cleanup/simplifying patches

[Henrik Nordström]

mån 2012-10-29 klockan 17:15 +0100 skrev Stefan Roese:

> This patchset tries to clean up and simplify the sunxi dram.c
> code a bit.

Thanks. The dram code is a bit odd, inherited from old Allwinner code
via the kernel source (CPU deep sleep standby/suspend code), modified
for this usage and adapted for A13.

Tom earlier made an attemt to make a nicer DRAM initialization, but
using hardwired values for the register values making it harder to
parameterize for different boards. This combined with a number of
changes needed for A13 made me switch to the older code published as
part of the kernel source and updating it for boot initialization and
A13 support.

Regards
Henrik

[Henrik Nordström]

mån 2012-10-29 klockan 17:15 +0100 skrev Stefan Roese:

> From: Stefan Roese <s...@denx.de>

>
>
> This patchset tries to clean up and simplify the sunxi dram.c
> code a bit.

All 8 patchsets looks correct to me and have been applied.

Regards
Henrik

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

No Upper-case (or CamelCase) in function names.

Signed-off-by: Stefan Roese <s...@denx.de>
---
arch/arm/cpu/armv7/sunxi/dram.c | 23 ++++++++++-------------
arch/arm/include/asm/arch-sunxi/dram.h | 4 ++--
board/sunxi/board.c | 4 ++--
board/sunxi/dram_a13_mid.c | 2 +-
board/sunxi/dram_a13_olinuxino.c | 2 +-
board/sunxi/dram_cubieboard.c | 2 +-
board/sunxi/dram_cubieboard_512.c | 2 +-
board/sunxi/dram_hackberry.c | 2 +-
board/sunxi/dram_mele_a1000.c | 2 +-
board/sunxi/dram_mini_x.c | 2 +-
10 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 201bee7..3b1301e 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -35,8 +35,6 @@
#define mctl_read_w(n) (*((volatile unsigned int *)(n)))
#define mctl_write_w(n,c) (*((volatile unsigned int *)(n)) = (c))

-// test-only: no uppercase function and variable names
-
static void mctl_ddr3_reset(void)
{
__u32 reg_val;
@@ -280,8 +278,7 @@ static void mctl_setup_dram_clock(__u32 clk)
sdelay(0x1000);
}

-// test-only: no upped case characters
-static int DRAMC_scan_readpipe(void)
+static int dramc_scan_readpipe(void)
{
__u32 reg_val;

@@ -303,7 +300,7 @@ static int DRAMC_scan_readpipe(void)
}

// test-only: cant this be done via DCLK_OUT_OFFSET (dram.h)??? (no #ifdef here)
-static void DRAMC_clock_output_en(__u32 on)
+static void dramc_clock_output_en(__u32 on)
{
__u32 reg_val;

@@ -330,7 +327,7 @@ static void DRAMC_clock_output_en(__u32 on)
}

// test-only: arghhh! clean-up this #ifdef mess!!!!
-static void DRAMC_set_autorefresh_cycle(__u32 clk)
+static void dramc_set_autorefresh_cycle(__u32 clk)
{
__u32 reg_val;
__u32 tmp_val;
@@ -369,7 +366,7 @@ else
/*
* Get DRAM Size in MB unit;
*/
-unsigned DRAMC_get_dram_size(void)
+unsigned dramc_get_dram_size(void)
{
__u32 reg_val;
__u32 dram_size;
@@ -402,7 +399,7 @@ unsigned DRAMC_get_dram_size(void)
return dram_size;
}

-int DRAMC_init(struct dram_para *para)
+int dramc_init(struct dram_para *para)
{
__u32 reg_val;
__s32 ret_val;
@@ -425,7 +422,7 @@ int DRAMC_init(struct dram_para *para)
mctl_set_drive();

/* dram clock off */
- DRAMC_clock_output_en(0);
+ dramc_clock_output_en(0);

#ifdef CONFIG_SUN4I
/* select dram controller 1 */
@@ -474,7 +471,7 @@ int DRAMC_init(struct dram_para *para)
#endif

/* dram clock on */
- DRAMC_clock_output_en(1);
+ dramc_clock_output_en(1);

sdelay(0x10);

@@ -500,7 +497,7 @@ int DRAMC_init(struct dram_para *para)
#endif

/* set refresh period */
- DRAMC_set_autorefresh_cycle(para->clock);
+ dramc_set_autorefresh_cycle(para->clock);

/* set timing parameters */
mctl_write_w(SDR_TPR0, para->tpr0);
@@ -544,7 +541,7 @@ int DRAMC_init(struct dram_para *para)

/* scan read pipe value */
mctl_itm_enable();
- ret_val = DRAMC_scan_readpipe();
+ ret_val = dramc_scan_readpipe();

if (ret_val < 0)
return 0;
@@ -552,5 +549,5 @@ int DRAMC_init(struct dram_para *para)
/* configure all host port */
mctl_configure_hostport();

- return DRAMC_get_dram_size();
+ return dramc_get_dram_size();
}
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 70cc250..b641cef 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -222,7 +222,7 @@ struct dram_para {
#define DQS_DRIFT_COMPENSATION 0

int sunxi_dram_init(void);
-unsigned DRAMC_get_dram_size(void);
-int DRAMC_init(struct dram_para *para);
+unsigned dramc_get_dram_size(void);
+int dramc_init(struct dram_para *para);

#endif /* _SUNXI_DRAM_H */
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 8d772c4..03de3d1 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -43,14 +43,14 @@ int board_init(void)
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = DRAMC_get_dram_size() * 1024 * 1024;
+ gd->bd->bi_dram[0].size = dramc_get_dram_size() * 1024 * 1024;
}

int dram_init(void)
{
gd->ram_size =
get_ram_size((long *)PHYS_SDRAM_1,
- DRAMC_get_dram_size() * 1024 * 1024);
+ dramc_get_dram_size() * 1024 * 1024);

return 0;
}
diff --git a/board/sunxi/dram_a13_mid.c b/board/sunxi/dram_a13_mid.c
index 7af0246..11c9a38 100644
--- a/board/sunxi/dram_a13_mid.c
+++ b/board/sunxi/dram_a13_mid.c
@@ -27,5 +27,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
diff --git a/board/sunxi/dram_a13_olinuxino.c b/board/sunxi/dram_a13_olinuxino.c
index 8099c1b..12b66d9 100644
--- a/board/sunxi/dram_a13_olinuxino.c
+++ b/board/sunxi/dram_a13_olinuxino.c
@@ -27,5 +27,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c
index 2c9e0c9..7e71b35 100644
--- a/board/sunxi/dram_cubieboard.c
+++ b/board/sunxi/dram_cubieboard.c
@@ -27,5 +27,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
diff --git a/board/sunxi/dram_cubieboard_512.c b/board/sunxi/dram_cubieboard_512.c
index f237504..3377fba 100644
--- a/board/sunxi/dram_cubieboard_512.c
+++ b/board/sunxi/dram_cubieboard_512.c
@@ -27,5 +27,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
diff --git a/board/sunxi/dram_hackberry.c b/board/sunxi/dram_hackberry.c
index 9587dde..5c6085c 100644
--- a/board/sunxi/dram_hackberry.c
+++ b/board/sunxi/dram_hackberry.c
@@ -27,5 +27,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
diff --git a/board/sunxi/dram_mele_a1000.c b/board/sunxi/dram_mele_a1000.c
index cc9e771..a6779b0 100644
--- a/board/sunxi/dram_mele_a1000.c
+++ b/board/sunxi/dram_mele_a1000.c
@@ -20,5 +20,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
diff --git a/board/sunxi/dram_mini_x.c b/board/sunxi/dram_mini_x.c
index 46a1dc8..3318a34 100644
--- a/board/sunxi/dram_mini_x.c
+++ b/board/sunxi/dram_mini_x.c
@@ -27,5 +27,5 @@ static struct dram_para dram_para = {

int sunxi_dram_init(void)
{
- return DRAMC_init(&dram_para);
+ return dramc_init(&dram_para);
}
--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Simplify dramc_set_autorefresh_cycle() by splitting it into different
version for sun4i und sun5i. The combined version was really ugly
and nearly unreadable.

Signed-off-by: Stefan Roese <s...@denx.de>

---

arch/arm/cpu/armv7/sunxi/dram.c | 44 +++++++++++++++++++++++------------------
1 file changed, 25 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 3db5a6b..2c4d5aa 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -248,43 +248,49 @@ static void dramc_clock_output_en(u32 on)
#endif
}

-// test-only: arghhh! clean-up this #ifdef mess!!!!
+#ifdef CONFIG_SUN4I
static void dramc_set_autorefresh_cycle(u32 clk)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
u32 reg_val;
u32 tmp_val;
-#ifdef CONFIG_SUN4I
u32 dram_size;

- dram_size = readl(&dram->dcr);
- dram_size >>= 3;
- dram_size &= 0x7;
-
if (clk < 600) {
+ dram_size = readl(&dram->dcr);
+ dram_size >>= 3;
+ dram_size &= 0x7;
if (dram_size <= 0x2)
- tmp_val = (131 * clk) >> 10;
+ reg_val = (131 * clk) >> 10;
else
- tmp_val = (336 * clk) >> 10;
- reg_val = tmp_val;
-#else
+ reg_val = (336 * clk) >> 10;
+
+ tmp_val = (7987 * clk) >> 10;
+ tmp_val = tmp_val * 9 - 200;
+ reg_val |= tmp_val << 8;
+ reg_val |= 0x8 << 24;
+ writel(reg_val, &dram->drr);
+ } else {
+ writel(0x0, &dram->drr);
+ }
+}
+#endif /* SUN4I */
+
+#ifdef CONFIG_SUN5I
+static void dramc_set_autorefresh_cycle(u32 clk)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+ u32 reg_val;
+ u32 tmp_val;
reg_val = 131;
-#endif

tmp_val = (7987 * clk) >> 10;
tmp_val = tmp_val * 9 - 200;
reg_val |= tmp_val << 8;
reg_val |= 0x8 << 24;
writel(reg_val, &dram->drr);
-#ifdef CONFIG_SUN4I
-}
-
-else
-{
- writel(0x0, &dram->drr);
-}
-#endif
}
+#endif /* SUN5I */

/*
* Get DRAM Size in MB unit;

--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Signed-off-by: Stefan Roese <s...@denx.de>
---

arch/arm/cpu/armv7/sunxi/dram.c | 149 ++++++++++------------------------------
1 file changed, 36 insertions(+), 113 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index f42fc32..ad7c98b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -42,64 +42,42 @@ static void mctl_ddr3_reset(void)
reg_val &= 0x3;

if (reg_val != 0) {
- reg_val = readl(SDR_CR);
- reg_val |= (0x1 << 12);
- writel(reg_val, SDR_CR);
+ setbits_le32(SDR_CR, 0x1 << 12);
sdelay(0x100);
- reg_val = readl(SDR_CR);
- reg_val &= ~(0x1 << 12);
- writel(reg_val, SDR_CR);
+ clrbits_le32(SDR_CR, 0x1 << 12);
} else
#endif
{
- reg_val = readl(SDR_CR);
- reg_val &= ~(0x1 << 12);
- writel(reg_val, SDR_CR);
+ clrbits_le32(SDR_CR, 0x1 << 12);
sdelay(0x100);
- reg_val = readl(SDR_CR);
- reg_val |= (0x1 << 12);
- writel(reg_val, SDR_CR);
+ setbits_le32(SDR_CR, 0x1 << 12);
}
}

static void mctl_set_drive(void)
{
- __u32 reg_val;
-
- reg_val = readl(SDR_CR);
- reg_val |= (0x6 << 12);
- reg_val |= 0xFFC;
- reg_val &= ~0x3;
- writel(reg_val, SDR_CR);
+ clrsetbits_le32(SDR_CR, 0x3, (0x6 << 12) | 0xFFC);
}

static void mctl_itm_disable(void)
{
- __u32 reg_val = 0x0;
-
- reg_val = readl(SDR_CCR);
- reg_val |= 0x1 << 28;
- writel(reg_val, SDR_CCR);
+ setbits_le32(SDR_CCR, 0x1 << 28);
}

static void mctl_itm_enable(void)
{
- __u32 reg_val = 0x0;
-
- reg_val = readl(SDR_CCR);
- reg_val &= ~(0x1 << 28);
- writel(reg_val, SDR_CCR);
+ clrbits_le32(SDR_CCR, 0x1 << 28);
}

static void mctl_enable_dll0(void)
{
- writel((readl(SDR_DLLCR0) & ~0x40000000) | 0x80000000, SDR_DLLCR0);
+ clrsetbits_le32(SDR_DLLCR0, 0x40000000, 0x80000000);
sdelay(0x100);

- writel(readl(SDR_DLLCR0) & ~0xC0000000, SDR_DLLCR0);
+ clrbits_le32(SDR_DLLCR0, 0xC0000000);
sdelay(0x1000);

- writel((readl(SDR_DLLCR0) & ~0x80000000) | 0x40000000, SDR_DLLCR0);
+ clrsetbits_le32(SDR_DLLCR0, 0x80000000, 0x40000000);
sdelay(0x1000);
}

@@ -123,22 +101,16 @@ static void mctl_enable_dllx(void)
i = 1;
}

- for (i = 1; i < n; i++) {
- writel((readl(SDR_DLLCR0 + (i << 2)) & ~0x40000000)
- | 0x80000000, SDR_DLLCR0 + (i << 2));
- }
+ for (i = 1; i < n; i++)
+ clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x40000000, 0x80000000);
sdelay(0x100);

- for (i = 1; i < n; i++) {
- writel(readl(SDR_DLLCR0 + (i << 2)) & ~0xC0000000,
- SDR_DLLCR0 + (i << 2));
- }
+ for (i = 1; i < n; i++)
+ clrbits_le32(SDR_DLLCR0 + (i << 2), 0xC0000000);
sdelay(0x1000);

- for (i = 1; i < n; i++) {
- writel((readl(SDR_DLLCR0 + (i << 2)) & ~0x80000000)
- | 0x40000000, SDR_DLLCR0 + (i << 2));
- }
+ for (i = 1; i < n; i++)
+ clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x80000000, 0x40000000);
sdelay(0x1000);
}

@@ -146,32 +118,11 @@ static void mctl_enable_dllx(void)
#if 0
static void mctl_disable_dll(void)
{
- __u32 reg_val;
-
- reg_val = readl(SDR_DLLCR0);
- reg_val &= ~(0x1 << 30);
- reg_val |= 0x1U << 31;
- writel(reg_val, SDR_DLLCR0);
-
- reg_val = readl(SDR_DLLCR1);
- reg_val &= ~(0x1 << 30);
- reg_val |= 0x1U << 31;
- writel(reg_val, SDR_DLLCR1);
-
- reg_val = readl(SDR_DLLCR2);
- reg_val &= ~(0x1 << 30);
- reg_val |= 0x1U << 31;
- writel(reg_val, SDR_DLLCR2);
-
- reg_val = readl(SDR_DLLCR3);
- reg_val &= ~(0x1 << 30);
- reg_val |= 0x1U << 31;
- writel(reg_val, SDR_DLLCR3);
-
- reg_val = readl(SDR_DLLCR4);
- reg_val &= ~(0x1 << 30);
- reg_val |= 0x1U << 31;
- writel(reg_val, SDR_DLLCR4);
+ clrsetbits_le32(SDR_DLLCR0, 0x1 << 30, 0x1U << 31);
+ clrsetbits_le32(SDR_DLLCR1, 0x1 << 30, 0x1U << 31);
+ clrsetbits_le32(SDR_DLLCR2, 0x1 << 30, 0x1U << 31);
+ clrsetbits_le32(SDR_DLLCR3, 0x1 << 30, 0x1U << 31);
+ clrsetbits_le32(SDR_DLLCR4, 0x1 << 30, 0x1U << 31);
}
#endif

@@ -225,22 +176,14 @@ static void mctl_setup_dram_clock(__u32 clk)
writel(reg_val, DRAM_CCM_SDRAM_PLL_REG);
sdelay(0x100000);

- reg_val = readl(DRAM_CCM_SDRAM_PLL_REG);
- reg_val |= 0x1 << 29;
- writel(reg_val, DRAM_CCM_SDRAM_PLL_REG);
+ setbits_le32(DRAM_CCM_SDRAM_PLL_REG, 0x1 << 29);

#ifdef CONFIG_SUN4I
/* reset GPS */
- reg_val = readl(DRAM_CCM_GPS_CLK_REG);
- reg_val &= ~0x3;
- writel(reg_val, DRAM_CCM_GPS_CLK_REG);
- reg_val = readl(DRAM_CCM_AHB_GATE_REG);
- reg_val |= (0x1 << 26);
- writel(reg_val, DRAM_CCM_AHB_GATE_REG);
+ clrbits_le32(DRAM_CCM_GPS_CLK_REG, 0x3);
+ setbits_le32(DRAM_CCM_AHB_GATE_REG, 0x1 << 26);
sdelay(0x20);
- reg_val = readl(DRAM_CCM_AHB_GATE_REG);
- reg_val &= ~(0x1 << 26);
- writel(reg_val, DRAM_CCM_AHB_GATE_REG);
+ clrbits_le32(DRAM_CCM_AHB_GATE_REG, 0x1 << 26);
#endif

/* setup MBUS clock */
@@ -251,22 +194,19 @@ static void mctl_setup_dram_clock(__u32 clk)
* open DRAMC AHB & DLL register clock
* close it first
*/
- reg_val = readl(DRAM_CCM_AHB_GATE_REG);
#ifdef CONFIG_SUN5I
- reg_val &= ~(0x3 << 14);
+ clrbits_le32(DRAM_CCM_AHB_GATE_REG, 0x3 << 14);
#else
- reg_val &= ~(0x1 << 14);
+ clrbits_le32(DRAM_CCM_AHB_GATE_REG, 0x1 << 14);
#endif
- writel(reg_val, DRAM_CCM_AHB_GATE_REG);
sdelay(0x1000);

/* then open it */
#ifdef CONFIG_SUN5I
- reg_val |= 0x3 << 14;
+ setbits_le32(DRAM_CCM_AHB_GATE_REG, 0x3 << 14);
#else
- reg_val |= 0x1 << 14;
+ setbits_le32(DRAM_CCM_AHB_GATE_REG, 0x1 << 14);
#endif
- writel(reg_val, DRAM_CCM_AHB_GATE_REG);
sdelay(0x1000);
}

@@ -275,9 +215,7 @@ static int dramc_scan_readpipe(void)
__u32 reg_val;

/* data training trigger */
- reg_val = readl(SDR_CCR);
- reg_val |= 0x1 << 30;
- writel(reg_val, SDR_CCR);
+ setbits_le32(SDR_CCR, 0x1 << 30);

/* check whether data training process is end */
while (readl(SDR_CCR) & (0x1 << 30))
@@ -294,27 +232,17 @@ static int dramc_scan_readpipe(void)

// test-only: cant this be done via DCLK_OUT_OFFSET (dram.h)??? (no #ifdef here)

static void dramc_clock_output_en(__u32 on)
{
- __u32 reg_val;
-
#ifdef CONFIG_SUN5I
- reg_val = readl(SDR_CR);
-
if (on)
- reg_val |= 0x1 << 16;
+ setbits_le32(SDR_CR, 0x1 << 16);
else
- reg_val &= ~(0x1 << 16);
-
- writel(reg_val, SDR_CR);
+ clrbits_le32(SDR_CR, 0x1 << 16);
#endif
#ifdef CONFIG_SUN4I
- reg_val = readl(DRAM_CCM_SDRAM_CLK_REG);
-
if (on)
- reg_val |= 0x1 << 15;
+ setbits_le32(DRAM_CCM_SDRAM_CLK_REG, 0x1 << 15);
else
- reg_val &= ~(0x1 << 15);
-
- writel(reg_val, DRAM_CCM_SDRAM_CLK_REG);
+ clrbits_le32(DRAM_CCM_SDRAM_CLK_REG, 0x1 << 15);
#endif
}

@@ -518,15 +446,10 @@ int dramc_init(struct dram_para *para)
writel(para->emr3, SDR_EMR3);

/* set DQS window mode */
- reg_val = readl(SDR_CCR);
- reg_val |= 0x1U << 14;
- reg_val &= ~(0x1U << 17);
- writel(reg_val, SDR_CCR);
+ clrsetbits_le32(SDR_CCR, 0x1U << 17, 0x1U << 14);

/* initial external DRAM */
- reg_val = readl(SDR_CCR);
- reg_val |= 0x1U << 31;
- writel(reg_val, SDR_CCR);
+ setbits_le32(SDR_CCR, 0x1U << 31);

while (readl(SDR_CCR) & (0x1U << 31))
;
--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>


This patchset tries to clean up and simplify the sunxi dram.c
code a bit.

All this is compile tested only. Testing on real hardware still
needs to be done. I'm still waiting on my TTL-USB adapter for the
console to do some real testing on my Cubieboard.

Thanks,
Stefan


Stefan Roese (8):
ARM: sunxi: Change upper case functions DRAMC_xxx() to dramc_xxx()
ARM: sunxi: dram.c: Use readl/writel instead of volatile accessor
macros
ARM: sunxi: dram.c: Use clrsetbits_le32() and friends for bit
manipulation
ARM: sunxi: dram.c: Simplify dram size calculation
ARM: sunxi: dram.c: Use u32 instead of __u32
ARM: sunxi: dram.c: Use struct instead of macros to access register
ARM: sunxi: dram.c: Remove unused code
ARM: sunxi: dram.c: Simplify dramc_set_autorefresh_cycle()

arch/arm/cpu/armv7/sunxi/dram.c | 339 ++++++++++++---------------------
arch/arm/include/asm/arch-sunxi/dram.h | 59 +-----
board/sunxi/board.c | 4 +-

board/sunxi/dram_a13_mid.c | 2 +-
board/sunxi/dram_a13_olinuxino.c | 2 +-
board/sunxi/dram_cubieboard.c | 2 +-
board/sunxi/dram_cubieboard_512.c | 2 +-
board/sunxi/dram_hackberry.c | 2 +-
board/sunxi/dram_mele_a1000.c | 2 +-
board/sunxi/dram_mini_x.c | 2 +-

10 files changed, 138 insertions(+), 278 deletions(-)

--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Signed-off-by: Stefan Roese <s...@denx.de>
---

arch/arm/cpu/armv7/sunxi/dram.c | 12 ------------
arch/arm/include/asm/arch-sunxi/dram.h | 6 ------
2 files changed, 18 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index d8da305..3db5a6b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -125,18 +125,6 @@ static void mctl_enable_dllx(void)
sdelay(0x1000);
}

-// test-only: not used at all, really needed???
-#if 0
-static void mctl_disable_dll(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
- int i;
-
- for (i = 0; i < 5; i++)
- clrsetbits_le32(&dram->dllcr[i], 0x1 << 30, 0x1U << 31);
-}
-#endif
-
static u32 hpcr_value[32] = {
#ifdef CONFIG_SUN5I
0, 0, 0, 0,
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index f2506f4..5f41f69 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -167,12 +167,6 @@ struct dram_para {
#define MR_CAS_LATENCY 2
#define MR_WRITE_RECOVERY 5

-// test-only: remove unused code
-/* For SUN5I I had tese set as follows for some reason
-#define MR_POWER_DOWN 0
-#define MR_CAS_LATENCY (9-4)
-*/
-
#define DQS_GATE_ON 1
#define DQS_DRIFT_COMPENSATION 0

--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Signed-off-by: Stefan Roese <s...@denx.de>
---

arch/arm/cpu/armv7/sunxi/dram.c | 172 +++++++++++++++++++---------------------
1 file changed, 82 insertions(+), 90 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 3b1301e..f42fc32 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -31,38 +31,34 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>

-// test-only: no volatile access, this should be converted to readl/writel
-#define mctl_read_w(n) (*((volatile unsigned int *)(n)))
-#define mctl_write_w(n,c) (*((volatile unsigned int *)(n)) = (c))

-
static void mctl_ddr3_reset(void)
{
__u32 reg_val;

#ifdef CONFIG_SUN4I
- mctl_write_w(TIMER_CPU_CFG_REG, 0);
- reg_val = mctl_read_w(TIMER_CPU_CFG_REG);
+ writel(0, TIMER_CPU_CFG_REG);
+ reg_val = readl(TIMER_CPU_CFG_REG);
reg_val >>= 6;

reg_val &= 0x3;

if (reg_val != 0) {

- reg_val = mctl_read_w(SDR_CR);
+ reg_val = readl(SDR_CR);
reg_val |= (0x1 << 12);
- mctl_write_w(SDR_CR, reg_val);
+ writel(reg_val, SDR_CR);
sdelay(0x100);
- reg_val = mctl_read_w(SDR_CR);
+ reg_val = readl(SDR_CR);
reg_val &= ~(0x1 << 12);
- mctl_write_w(SDR_CR, reg_val);
+ writel(reg_val, SDR_CR);
} else
#endif
{
- reg_val = mctl_read_w(SDR_CR);
+ reg_val = readl(SDR_CR);
reg_val &= ~(0x1 << 12);
- mctl_write_w(SDR_CR, reg_val);
+ writel(reg_val, SDR_CR);
sdelay(0x100);
- reg_val = mctl_read_w(SDR_CR);
+ reg_val = readl(SDR_CR);
reg_val |= (0x1 << 12);
- mctl_write_w(SDR_CR, reg_val);
+ writel(reg_val, SDR_CR);
}
}

@@ -70,42 +66,40 @@ static void mctl_set_drive(void)
{
__u32 reg_val;

- reg_val = mctl_read_w(SDR_CR);
+ reg_val = readl(SDR_CR);
reg_val |= (0x6 << 12);
reg_val |= 0xFFC;
reg_val &= ~0x3;
- mctl_write_w(SDR_CR, reg_val);
+ writel(reg_val, SDR_CR);
}

static void mctl_itm_disable(void)
{
__u32 reg_val = 0x0;

- reg_val = mctl_read_w(SDR_CCR);
+ reg_val = readl(SDR_CCR);
reg_val |= 0x1 << 28;
- mctl_write_w(SDR_CCR, reg_val);
+ writel(reg_val, SDR_CCR);
}

static void mctl_itm_enable(void)
{
__u32 reg_val = 0x0;

- reg_val = mctl_read_w(SDR_CCR);
+ reg_val = readl(SDR_CCR);
reg_val &= ~(0x1 << 28);
- mctl_write_w(SDR_CCR, reg_val);
+ writel(reg_val, SDR_CCR);
}

static void mctl_enable_dll0(void)
{
- mctl_write_w(SDR_DLLCR0,
- (mctl_read_w(SDR_DLLCR0) & ~0x40000000) | 0x80000000);
+ writel((readl(SDR_DLLCR0) & ~0x40000000) | 0x80000000, SDR_DLLCR0);
sdelay(0x100);

- mctl_write_w(SDR_DLLCR0, mctl_read_w(SDR_DLLCR0) & ~0xC0000000);
+ writel(readl(SDR_DLLCR0) & ~0xC0000000, SDR_DLLCR0);
sdelay(0x1000);

- mctl_write_w(SDR_DLLCR0,
- (mctl_read_w(SDR_DLLCR0) & ~0x80000000) | 0x40000000);
+ writel((readl(SDR_DLLCR0) & ~0x80000000) | 0x40000000, SDR_DLLCR0);
sdelay(0x1000);
}

@@ -118,7 +112,7 @@ static void mctl_enable_dllx(void)
__u32 n;
__u32 bus_width;

- bus_width = mctl_read_w(SDR_DCR);
+ bus_width = readl(SDR_DCR);
bus_width >>= 6;
bus_width &= 7;

@@ -130,22 +124,20 @@ static void mctl_enable_dllx(void)

}

for (i = 1; i < n; i++) {

- mctl_write_w(SDR_DLLCR0 + (i << 2),
- (mctl_read_w(SDR_DLLCR0 + (i << 2)) & ~0x40000000)
- | 0x80000000);
+ writel((readl(SDR_DLLCR0 + (i << 2)) & ~0x40000000)
+ | 0x80000000, SDR_DLLCR0 + (i << 2));
}
sdelay(0x100);

for (i = 1; i < n; i++) {

- mctl_write_w(SDR_DLLCR0 + (i << 2),
- mctl_read_w(SDR_DLLCR0 + (i << 2)) & ~0xC0000000);
+ writel(readl(SDR_DLLCR0 + (i << 2)) & ~0xC0000000,
+ SDR_DLLCR0 + (i << 2));
}
sdelay(0x1000);

for (i = 1; i < n; i++) {

- mctl_write_w(SDR_DLLCR0 + (i << 2),
- (mctl_read_w(SDR_DLLCR0 + (i << 2)) & ~0x80000000)
- | 0x40000000);
+ writel((readl(SDR_DLLCR0 + (i << 2)) & ~0x80000000)
+ | 0x40000000, SDR_DLLCR0 + (i << 2));
}
sdelay(0x1000);
}
@@ -156,30 +148,30 @@ static void mctl_disable_dll(void)
{
__u32 reg_val;

- reg_val = mctl_read_w(SDR_DLLCR0);
+ reg_val = readl(SDR_DLLCR0);
reg_val &= ~(0x1 << 30);
reg_val |= 0x1U << 31;
- mctl_write_w(SDR_DLLCR0, reg_val);
+ writel(reg_val, SDR_DLLCR0);

- reg_val = mctl_read_w(SDR_DLLCR1);
+ reg_val = readl(SDR_DLLCR1);
reg_val &= ~(0x1 << 30);
reg_val |= 0x1U << 31;
- mctl_write_w(SDR_DLLCR1, reg_val);
+ writel(reg_val, SDR_DLLCR1);

- reg_val = mctl_read_w(SDR_DLLCR2);
+ reg_val = readl(SDR_DLLCR2);
reg_val &= ~(0x1 << 30);
reg_val |= 0x1U << 31;
- mctl_write_w(SDR_DLLCR2, reg_val);
+ writel(reg_val, SDR_DLLCR2);

- reg_val = mctl_read_w(SDR_DLLCR3);
+ reg_val = readl(SDR_DLLCR3);
reg_val &= ~(0x1 << 30);
reg_val |= 0x1U << 31;
- mctl_write_w(SDR_DLLCR3, reg_val);
+ writel(reg_val, SDR_DLLCR3);

- reg_val = mctl_read_w(SDR_DLLCR4);
+ reg_val = readl(SDR_DLLCR4);
reg_val &= ~(0x1 << 30);
reg_val |= 0x1U << 31;
- mctl_write_w(SDR_DLLCR4, reg_val);
+ writel(reg_val, SDR_DLLCR4);
}
#endif

@@ -211,7 +203,7 @@ static void mctl_configure_hostport(void)
__u32 i;

for (i = 0; i < 32; i++)
- mctl_write_w(SDR_HPCR + (i << 2), hpcr_value[i]);
+ writel(hpcr_value[i], SDR_HPCR + (i << 2));
}

static void mctl_setup_dram_clock(__u32 clk)
@@ -219,7 +211,7 @@ static void mctl_setup_dram_clock(__u32 clk)
__u32 reg_val;

/* setup DRAM PLL */
- reg_val = mctl_read_w(DRAM_CCM_SDRAM_PLL_REG);
+ reg_val = readl(DRAM_CCM_SDRAM_PLL_REG);
reg_val &= ~0x3;
reg_val |= 0x1; /* m factor */
reg_val &= ~(0x3 << 4);
@@ -230,42 +222,42 @@ static void mctl_setup_dram_clock(__u32 clk)
reg_val |= 0x1 << 16; /* p factor */
reg_val &= ~(0x1 << 29); /* PLL on */
reg_val |= (__u32) 0x1 << 31; /* PLL En */
- mctl_write_w(DRAM_CCM_SDRAM_PLL_REG, reg_val);
+ writel(reg_val, DRAM_CCM_SDRAM_PLL_REG);
sdelay(0x100000);

- reg_val = mctl_read_w(DRAM_CCM_SDRAM_PLL_REG);
+ reg_val = readl(DRAM_CCM_SDRAM_PLL_REG);
reg_val |= 0x1 << 29;
- mctl_write_w(DRAM_CCM_SDRAM_PLL_REG, reg_val);
+ writel(reg_val, DRAM_CCM_SDRAM_PLL_REG);

#ifdef CONFIG_SUN4I
/* reset GPS */

- reg_val = mctl_read_w(DRAM_CCM_GPS_CLK_REG);
+ reg_val = readl(DRAM_CCM_GPS_CLK_REG);
reg_val &= ~0x3;
- mctl_write_w(DRAM_CCM_GPS_CLK_REG, reg_val);
- reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG);
+ writel(reg_val, DRAM_CCM_GPS_CLK_REG);
+ reg_val = readl(DRAM_CCM_AHB_GATE_REG);
reg_val |= (0x1 << 26);
- mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val);
+ writel(reg_val, DRAM_CCM_AHB_GATE_REG);
sdelay(0x20);
- reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG);
+ reg_val = readl(DRAM_CCM_AHB_GATE_REG);
reg_val &= ~(0x1 << 26);
- mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val);
+ writel(reg_val, DRAM_CCM_AHB_GATE_REG);

#endif

/* setup MBUS clock */

reg_val = (0x1 << 31) | (0x2 << 24) | (0x1);
- mctl_write_w(DRAM_CCM_MUS_CLK_REG, reg_val);
+ writel(reg_val, DRAM_CCM_MUS_CLK_REG);

/*

* open DRAMC AHB & DLL register clock
* close it first
*/

- reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG);
+ reg_val = readl(DRAM_CCM_AHB_GATE_REG);
#ifdef CONFIG_SUN5I
reg_val &= ~(0x3 << 14);
#else
reg_val &= ~(0x1 << 14);
#endif
- mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val);
+ writel(reg_val, DRAM_CCM_AHB_GATE_REG);

sdelay(0x1000);

/* then open it */

@@ -274,7 +266,7 @@ static void mctl_setup_dram_clock(__u32 clk)
#else
reg_val |= 0x1 << 14;
#endif
- mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val);
+ writel(reg_val, DRAM_CCM_AHB_GATE_REG);
sdelay(0x1000);
}

@@ -283,16 +275,16 @@ static int dramc_scan_readpipe(void)

__u32 reg_val;

/* data training trigger */

- reg_val = mctl_read_w(SDR_CCR);
+ reg_val = readl(SDR_CCR);
reg_val |= 0x1 << 30;
- mctl_write_w(SDR_CCR, reg_val);
+ writel(reg_val, SDR_CCR);

/* check whether data training process is end */

- while (mctl_read_w(SDR_CCR) & (0x1 << 30))
+ while (readl(SDR_CCR) & (0x1 << 30))
;

/* check data training result */
- reg_val = mctl_read_w(SDR_CSR);
+ reg_val = readl(SDR_CSR);
if (reg_val & (0x1 << 20))
return -1;

@@ -305,24 +297,24 @@ static void dramc_clock_output_en(__u32 on)
__u32 reg_val;

#ifdef CONFIG_SUN5I
- reg_val = mctl_read_w(SDR_CR);
+ reg_val = readl(SDR_CR);

if (on)
reg_val |= 0x1 << 16;
else
reg_val &= ~(0x1 << 16);

- mctl_write_w(SDR_CR, reg_val);
+ writel(reg_val, SDR_CR);
#endif
#ifdef CONFIG_SUN4I
- reg_val = mctl_read_w(DRAM_CCM_SDRAM_CLK_REG);
+ reg_val = readl(DRAM_CCM_SDRAM_CLK_REG);

if (on)
reg_val |= 0x1 << 15;
else
reg_val &= ~(0x1 << 15);

- mctl_write_w(DRAM_CCM_SDRAM_CLK_REG, reg_val);
+ writel(reg_val, DRAM_CCM_SDRAM_CLK_REG);
#endif
}

@@ -334,7 +326,7 @@ static void dramc_set_autorefresh_cycle(__u32 clk)
#ifdef CONFIG_SUN4I
__u32 dram_size;

- dram_size = mctl_read_w(SDR_DCR);
+ dram_size = readl(SDR_DCR);
dram_size >>= 3;
dram_size &= 0x7;

@@ -352,13 +344,13 @@ static void dramc_set_autorefresh_cycle(__u32 clk)

tmp_val = tmp_val * 9 - 200;
reg_val |= tmp_val << 8;
reg_val |= 0x8 << 24;

- mctl_write_w(SDR_DRR, reg_val);
+ writel(reg_val, SDR_DRR);
#ifdef CONFIG_SUN4I
}

else
{
- mctl_write_w(SDR_DRR, 0x0);
+ writel(0x0, SDR_DRR);
}
#endif
}
@@ -372,7 +364,7 @@ unsigned dramc_get_dram_size(void)
__u32 dram_size;
__u32 chip_den;

- reg_val = mctl_read_w(SDR_DCR);
+ reg_val = readl(SDR_DCR);
chip_den = (reg_val >> 3) & 0x7;

// test-only: use an algorythm, like dram_size = (32 << chip_den)
@@ -414,7 +406,7 @@ int dramc_init(struct dram_para *para)
#ifdef CONFIG_SUN5I
// test-only: new code? does it work? change or remove comment
/* This is new unknown code! */
- mctl_write_w(SDR_0x23c, 0);
+ writel(0, SDR_0x23c);
#endif

/* reset external DRAM */
@@ -426,7 +418,7 @@ int dramc_init(struct dram_para *para)

#ifdef CONFIG_SUN4I
/* select dram controller 1 */

- mctl_write_w(SDR_SCSR, 0x16237495);
+ writel(0x16237495, SDR_SCSR);
#endif

mctl_itm_disable();
@@ -460,14 +452,14 @@ int dramc_init(struct dram_para *para)
reg_val |= 0x1 << 12;
reg_val |= ((0x1) & 0x3) << 13;

- mctl_write_w(SDR_DCR, reg_val);
+ writel(reg_val, SDR_DCR);

#ifdef CONFIG_SUN5I
/* set odt impendance divide ratio */
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;
- mctl_write_w(SDR_ZQCR0, reg_val);
+ writel(reg_val, SDR_ZQCR0);

#endif

/* dram clock on */

@@ -475,7 +467,7 @@ int dramc_init(struct dram_para *para)

sdelay(0x10);

- while (mctl_read_w(SDR_CCR) & (0x1U << 31))
+ while (readl(SDR_CCR) & (0x1U << 31))
;

mctl_enable_dllx();
@@ -485,7 +477,7 @@ int dramc_init(struct dram_para *para)
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;
- mctl_write_w(SDR_ZQCR0, reg_val);
+ writel(reg_val, SDR_ZQCR0);
#endif

#ifdef CONFIG_SUN4I
@@ -493,16 +485,16 @@ int dramc_init(struct dram_para *para)
reg_val = 0x00cc0000;
reg_val |= (para->odt_en) & 0x3;
reg_val |= ((para->odt_en) & 0x3) << 30;
- mctl_write_w(SDR_IOCR, reg_val);
+ writel(reg_val, SDR_IOCR);

#endif

/* set refresh period */

dramc_set_autorefresh_cycle(para->clock);

/* set timing parameters */

- mctl_write_w(SDR_TPR0, para->tpr0);
- mctl_write_w(SDR_TPR1, para->tpr1);
- mctl_write_w(SDR_TPR2, para->tpr2);
+ writel(para->tpr0, SDR_TPR0);
+ writel(para->tpr1, SDR_TPR1);
+ writel(para->tpr2, SDR_TPR2);

/* set mode register */
if (para->type == 3) {
@@ -519,24 +511,24 @@ int dramc_init(struct dram_para *para)
reg_val |= para->cas << 4;
reg_val |= 0x5 << 9;
}
- mctl_write_w(SDR_MR, reg_val);
+ writel(reg_val, SDR_MR);

- mctl_write_w(SDR_EMR, para->emr1);
- mctl_write_w(SDR_EMR2, para->emr2);
- mctl_write_w(SDR_EMR3, para->emr3);
+ writel(para->emr1, SDR_EMR);
+ writel(para->emr2, SDR_EMR2);
+ writel(para->emr3, SDR_EMR3);

/* set DQS window mode */

- reg_val = mctl_read_w(SDR_CCR);
+ reg_val = readl(SDR_CCR);
reg_val |= 0x1U << 14;
reg_val &= ~(0x1U << 17);
- mctl_write_w(SDR_CCR, reg_val);
+ writel(reg_val, SDR_CCR);

/* initial external DRAM */

- reg_val = mctl_read_w(SDR_CCR);
+ reg_val = readl(SDR_CCR);
reg_val |= 0x1U << 31;
- mctl_write_w(SDR_CCR, reg_val);
+ writel(reg_val, SDR_CCR);

- while (mctl_read_w(SDR_CCR) & (0x1U << 31))
+ while (readl(SDR_CCR) & (0x1U << 31))
;

/* scan read pipe value */

--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Also an __s32 variable is switched to int which seems more correct.

Signed-off-by: Stefan Roese <s...@denx.de>
---

arch/arm/cpu/armv7/sunxi/dram.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 289e814..53f2ae9 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -33,7 +33,7 @@

static void mctl_ddr3_reset(void)
{
- __u32 reg_val;
+ u32 reg_val;

#ifdef CONFIG_SUN4I
writel(0, TIMER_CPU_CFG_REG);
@@ -86,9 +86,9 @@ static void mctl_enable_dll0(void)
*/
static void mctl_enable_dllx(void)
{
- __u32 i = 0;
- __u32 n;
- __u32 bus_width;
+ u32 i = 0;
+ u32 n;
+ u32 bus_width;

bus_width = readl(SDR_DCR);
bus_width >>= 6;

@@ -126,7 +126,7 @@ static void mctl_disable_dll(void)
}
#endif

-static __u32 hpcr_value[32] = {
+static u32 hpcr_value[32] = {

#ifdef CONFIG_SUN5I
0, 0, 0, 0,

0, 0, 0, 0,
@@ -151,15 +151,15 @@ static __u32 hpcr_value[32] = {

static void mctl_configure_hostport(void)
{
- __u32 i;
+ u32 i;

for (i = 0; i < 32; i++)

writel(hpcr_value[i], SDR_HPCR + (i << 2));
}

-static void mctl_setup_dram_clock(__u32 clk)
+static void mctl_setup_dram_clock(u32 clk)
{
- __u32 reg_val;
+ u32 reg_val;

/* setup DRAM PLL */

reg_val = readl(DRAM_CCM_SDRAM_PLL_REG);
@@ -172,7 +172,7 @@ static void mctl_setup_dram_clock(__u32 clk)
reg_val &= ~(0x3 << 16);

reg_val |= 0x1 << 16; /* p factor */
reg_val &= ~(0x1 << 29); /* PLL on */

- reg_val |= (__u32) 0x1 << 31; /* PLL En */
+ reg_val |= (u32) 0x1 << 31; /* PLL En */
writel(reg_val, DRAM_CCM_SDRAM_PLL_REG);
sdelay(0x100000);

@@ -212,7 +212,7 @@ static void mctl_setup_dram_clock(__u32 clk)

static int dramc_scan_readpipe(void)
{
- __u32 reg_val;
+ u32 reg_val;

/* data training trigger */

setbits_le32(SDR_CCR, 0x1 << 30);
@@ -230,7 +230,7 @@ static int dramc_scan_readpipe(void)

}

// test-only: cant this be done via DCLK_OUT_OFFSET (dram.h)??? (no #ifdef here)

-static void dramc_clock_output_en(__u32 on)
+static void dramc_clock_output_en(u32 on)
{
#ifdef CONFIG_SUN5I
if (on)
@@ -247,12 +247,12 @@ static void dramc_clock_output_en(__u32 on)

}

// test-only: arghhh! clean-up this #ifdef mess!!!!

-static void dramc_set_autorefresh_cycle(__u32 clk)
+static void dramc_set_autorefresh_cycle(u32 clk)
{
- __u32 reg_val;
- __u32 tmp_val;

+ u32 reg_val;
+ u32 tmp_val;

#ifdef CONFIG_SUN4I
- __u32 dram_size;
+ u32 dram_size;

dram_size = readl(SDR_DCR);
dram_size >>= 3;

@@ -288,9 +288,9 @@ else
*/
unsigned dramc_get_dram_size(void)
{
- __u32 reg_val;
- __u32 dram_size;
- __u32 chip_den;
+ u32 reg_val;
+ u32 dram_size;
+ u32 chip_den;

reg_val = readl(SDR_DCR);
chip_den = (reg_val >> 3) & 0x7;

@@ -309,8 +309,8 @@ unsigned dramc_get_dram_size(void)

int dramc_init(struct dram_para *para)
{
- __u32 reg_val;
- __s32 ret_val;
+ u32 reg_val;
+ int ret_val;

/* check input dram parameter structure */
if (!para)
--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Signed-off-by: Stefan Roese <s...@denx.de>
---

arch/arm/cpu/armv7/sunxi/dram.c | 117 +++++++++++++++++++--------------
arch/arm/include/asm/arch-sunxi/dram.h | 49 +-------------
2 files changed, 69 insertions(+), 97 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 53f2ae9..d8da305 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -33,51 +33,61 @@

static void mctl_ddr3_reset(void)
{
- u32 reg_val;
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;

#ifdef CONFIG_SUN4I
+ u32 reg_val;
+
writel(0, TIMER_CPU_CFG_REG);

reg_val = readl(TIMER_CPU_CFG_REG);
reg_val >>= 6;
reg_val &= 0x3;

if (reg_val != 0) {

- setbits_le32(SDR_CR, 0x1 << 12);
+ setbits_le32(&dram->mcr, 0x1 << 12);
sdelay(0x100);
- clrbits_le32(SDR_CR, 0x1 << 12);
+ clrbits_le32(&dram->mcr, 0x1 << 12);
} else
#endif
{
- clrbits_le32(SDR_CR, 0x1 << 12);
+ clrbits_le32(&dram->mcr, 0x1 << 12);
sdelay(0x100);
- setbits_le32(SDR_CR, 0x1 << 12);
+ setbits_le32(&dram->mcr, 0x1 << 12);
}
}

static void mctl_set_drive(void)
{
- clrsetbits_le32(SDR_CR, 0x3, (0x6 << 12) | 0xFFC);
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+
+ clrsetbits_le32(&dram->mcr, 0x3, (0x6 << 12) | 0xFFC);
}

static void mctl_itm_disable(void)
{
- setbits_le32(SDR_CCR, 0x1 << 28);
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+
+ setbits_le32(&dram->ccr, 0x1 << 28);
}

static void mctl_itm_enable(void)
{
- clrbits_le32(SDR_CCR, 0x1 << 28);
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+
+ clrbits_le32(&dram->ccr, 0x1 << 28);
}

static void mctl_enable_dll0(void)
{
- clrsetbits_le32(SDR_DLLCR0, 0x40000000, 0x80000000);
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+
+ clrsetbits_le32(&dram->dllcr[0], 0x40000000, 0x80000000);
sdelay(0x100);

- clrbits_le32(SDR_DLLCR0, 0xC0000000);
+ clrbits_le32(&dram->dllcr[0], 0xC0000000);
sdelay(0x1000);

- clrsetbits_le32(SDR_DLLCR0, 0x80000000, 0x40000000);
+ clrsetbits_le32(&dram->dllcr[0], 0x80000000, 0x40000000);
sdelay(0x1000);
}

@@ -86,11 +96,12 @@ static void mctl_enable_dll0(void)
*/
static void mctl_enable_dllx(void)
{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
u32 i = 0;
u32 n;
u32 bus_width;

- bus_width = readl(SDR_DCR);
+ bus_width = readl(&dram->dcr);

bus_width >>= 6;
bus_width &= 7;

@@ -102,15 +113,15 @@ static void mctl_enable_dllx(void)

}

for (i = 1; i < n; i++)

- clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x40000000, 0x80000000);
+ clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);

sdelay(0x100);

for (i = 1; i < n; i++)

- clrbits_le32(SDR_DLLCR0 + (i << 2), 0xC0000000);
+ clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);

sdelay(0x1000);

for (i = 1; i < n; i++)

- clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x80000000, 0x40000000);
+ clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);
sdelay(0x1000);
}

@@ -118,11 +129,11 @@ static void mctl_enable_dllx(void)

#if 0
static void mctl_disable_dll(void)
{

- clrsetbits_le32(SDR_DLLCR0, 0x1 << 30, 0x1U << 31);
- clrsetbits_le32(SDR_DLLCR1, 0x1 << 30, 0x1U << 31);
- clrsetbits_le32(SDR_DLLCR2, 0x1 << 30, 0x1U << 31);
- clrsetbits_le32(SDR_DLLCR3, 0x1 << 30, 0x1U << 31);
- clrsetbits_le32(SDR_DLLCR4, 0x1 << 30, 0x1U << 31);
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+ int i;
+
+ for (i = 0; i < 5; i++)
+ clrsetbits_le32(&dram->dllcr[i], 0x1 << 30, 0x1U << 31);
}
#endif

@@ -151,10 +162,11 @@ static u32 hpcr_value[32] = {

static void mctl_configure_hostport(void)
{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;

u32 i;

for (i = 0; i < 32; i++)

- writel(hpcr_value[i], SDR_HPCR + (i << 2));
+ writel(hpcr_value[i], &dram->hpcr[i]);
}

static void mctl_setup_dram_clock(u32 clk)
@@ -212,49 +224,52 @@ static void mctl_setup_dram_clock(u32 clk)

static int dramc_scan_readpipe(void)
{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;

u32 reg_val;

/* data training trigger */

- setbits_le32(SDR_CCR, 0x1 << 30);
+ setbits_le32(&dram->ccr, 0x1 << 30);

/* check whether data training process is end */

- while (readl(SDR_CCR) & (0x1 << 30))
+ while (readl(&dram->ccr) & (0x1 << 30))

;

/* check data training result */

- reg_val = readl(SDR_CSR);
+ reg_val = readl(&dram->csr);

if (reg_val & (0x1 << 20))
return -1;

return 0;
}

-// test-only: cant this be done via DCLK_OUT_OFFSET (dram.h)??? (no #ifdef here)

static void dramc_clock_output_en(u32 on)
{
#ifdef CONFIG_SUN5I

+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
+
if (on)
- setbits_le32(SDR_CR, 0x1 << 16);
+ setbits_le32(&dram->mcr, 0x1 << DCLK_OUT_OFFSET);
else
- clrbits_le32(SDR_CR, 0x1 << 16);
+ clrbits_le32(&dram->mcr, 0x1 << DCLK_OUT_OFFSET);
#endif
#ifdef CONFIG_SUN4I
if (on)
- setbits_le32(DRAM_CCM_SDRAM_CLK_REG, 0x1 << 15);
+ setbits_le32(DRAM_CCM_SDRAM_CLK_REG, 0x1 << DCLK_OUT_OFFSET);
else
- clrbits_le32(DRAM_CCM_SDRAM_CLK_REG, 0x1 << 15);
+ clrbits_le32(DRAM_CCM_SDRAM_CLK_REG, 0x1 << DCLK_OUT_OFFSET);
#endif

}

// test-only: arghhh! clean-up this #ifdef mess!!!!

static void dramc_set_autorefresh_cycle(u32 clk)
{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
u32 reg_val;
u32 tmp_val;
#ifdef CONFIG_SUN4I
u32 dram_size;

- dram_size = readl(SDR_DCR);

+ dram_size = readl(&dram->dcr);

dram_size >>= 3;
dram_size &= 0x7;

@@ -272,13 +287,13 @@ static void dramc_set_autorefresh_cycle(u32 clk)

tmp_val = tmp_val * 9 - 200;
reg_val |= tmp_val << 8;
reg_val |= 0x8 << 24;

- writel(reg_val, SDR_DRR);
+ writel(reg_val, &dram->drr);
#ifdef CONFIG_SUN4I
}

else
{
- writel(0x0, SDR_DRR);
+ writel(0x0, &dram->drr);
}
#endif
}
@@ -288,11 +303,12 @@ else
*/
unsigned dramc_get_dram_size(void)
{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
u32 reg_val;
u32 dram_size;
u32 chip_den;

- reg_val = readl(SDR_DCR);
+ reg_val = readl(&dram->dcr);

chip_den = (reg_val >> 3) & 0x7;

dram_size = min(1024, 32 << chip_den);
@@ -309,6 +325,7 @@ unsigned dramc_get_dram_size(void)

int dramc_init(struct dram_para *para)
{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
u32 reg_val;
int ret_val;

@@ -322,7 +339,7 @@ int dramc_init(struct dram_para *para)

#ifdef CONFIG_SUN5I
// test-only: new code? does it work? change or remove comment
/* This is new unknown code! */

- writel(0, SDR_0x23c);
+ writel(0, &dram->reg_23c);

#endif

/* reset external DRAM */

@@ -334,7 +351,7 @@ int dramc_init(struct dram_para *para)

#ifdef CONFIG_SUN4I
/* select dram controller 1 */

- writel(0x16237495, SDR_SCSR);
+ writel(0x16237495, &dram->csel);
#endif

mctl_itm_disable();
@@ -368,14 +385,14 @@ int dramc_init(struct dram_para *para)

reg_val |= 0x1 << 12;
reg_val |= ((0x1) & 0x3) << 13;

- writel(reg_val, SDR_DCR);
+ writel(reg_val, &dram->dcr);

#ifdef CONFIG_SUN5I
/* set odt impendance divide ratio */
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;

- writel(reg_val, SDR_ZQCR0);
+ writel(reg_val, &dram->zqcr0);

#endif

/* dram clock on */

@@ -383,7 +400,7 @@ int dramc_init(struct dram_para *para)

sdelay(0x10);

- while (readl(SDR_CCR) & (0x1U << 31))
+ while (readl(&dram->ccr) & (0x1U << 31))
;

mctl_enable_dllx();
@@ -393,7 +410,7 @@ int dramc_init(struct dram_para *para)

reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;

- writel(reg_val, SDR_ZQCR0);
+ writel(reg_val, &dram->zqcr0);
#endif

#ifdef CONFIG_SUN4I
@@ -401,16 +418,16 @@ int dramc_init(struct dram_para *para)

reg_val = 0x00cc0000;
reg_val |= (para->odt_en) & 0x3;
reg_val |= ((para->odt_en) & 0x3) << 30;

- writel(reg_val, SDR_IOCR);
+ writel(reg_val, &dram->iocr);

#endif

/* set refresh period */
dramc_set_autorefresh_cycle(para->clock);

/* set timing parameters */

- writel(para->tpr0, SDR_TPR0);
- writel(para->tpr1, SDR_TPR1);
- writel(para->tpr2, SDR_TPR2);
+ writel(para->tpr0, &dram->tpr0);
+ writel(para->tpr1, &dram->tpr1);
+ writel(para->tpr2, &dram->tpr2);

/* set mode register */
if (para->type == 3) {

@@ -427,19 +444,19 @@ int dramc_init(struct dram_para *para)

reg_val |= para->cas << 4;
reg_val |= 0x5 << 9;
}

- writel(reg_val, SDR_MR);
+ writel(reg_val, &dram->mr);

- writel(para->emr1, SDR_EMR);
- writel(para->emr2, SDR_EMR2);
- writel(para->emr3, SDR_EMR3);
+ writel(para->emr1, &dram->emr);
+ writel(para->emr2, &dram->emr2);
+ writel(para->emr3, &dram->emr3);

/* set DQS window mode */

- clrsetbits_le32(SDR_CCR, 0x1U << 17, 0x1U << 14);
+ clrsetbits_le32(&dram->ccr, 0x1U << 17, 0x1U << 14);

/* initial external DRAM */

- setbits_le32(SDR_CCR, 0x1U << 31);
+ setbits_le32(&dram->ccr, 0x1U << 31);

- while (readl(SDR_CCR) & (0x1U << 31))
+ while (readl(&dram->ccr) & (0x1U << 31))

;

/* scan read pipe value */

diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index b641cef..f2506f4 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -40,51 +40,6 @@
#define DRAM_CCM_MUS_CLK_REG (DRAM_CCM_BASE + 0x15c)
#define TIMER_CPU_CFG_REG (DRAM_TIMER_BASE + 0x13c)

-// test-only: these defines need to be converted to a struct
-#define SDR_CCR (DRAMC_IO_BASE + 0x00)
-#define SDR_DCR (DRAMC_IO_BASE + 0x04)
-#define SDR_IOCR (DRAMC_IO_BASE + 0x08)
-#define SDR_CSR (DRAMC_IO_BASE + 0x0c)
-#define SDR_DRR (DRAMC_IO_BASE + 0x10)
-#define SDR_TPR0 (DRAMC_IO_BASE + 0x14)
-#define SDR_TPR1 (DRAMC_IO_BASE + 0x18)
-#define SDR_TPR2 (DRAMC_IO_BASE + 0x1c)
-#define SDR_RSLR0 (DRAMC_IO_BASE + 0x4c)
-#define SDR_RSLR1 (DRAMC_IO_BASE + 0x50)
-#define SDR_RDQSGR (DRAMC_IO_BASE + 0x5c)
-#define SDR_ODTCR (DRAMC_IO_BASE + 0x98)
-#define SDR_DTR0 (DRAMC_IO_BASE + 0x9c)
-#define SDR_DTR1 (DRAMC_IO_BASE + 0xa0)
-#define SDR_DTAR (DRAMC_IO_BASE + 0xa4)
-#define SDR_ZQCR0 (DRAMC_IO_BASE + 0xa8)
-#define SDR_ZQCR1 (DRAMC_IO_BASE + 0xac)
-#define SDR_ZQSR (DRAMC_IO_BASE + 0xb0)
-#define SDR_IDCR (DRAMC_IO_BASE + 0xb4)
-#define SDR_MR (DRAMC_IO_BASE + 0x1f0)
-#define SDR_EMR (DRAMC_IO_BASE + 0x1f4)
-#define SDR_EMR2 (DRAMC_IO_BASE + 0x1f8)
-#define SDR_EMR3 (DRAMC_IO_BASE + 0x1fc)
-#define SDR_DLLCR (DRAMC_IO_BASE + 0x200)
-#define SDR_DLLCR0 (DRAMC_IO_BASE + 0x204)
-#define SDR_DLLCR1 (DRAMC_IO_BASE + 0x208)
-#define SDR_DLLCR2 (DRAMC_IO_BASE + 0x20c)
-#define SDR_DLLCR3 (DRAMC_IO_BASE + 0x210)
-#define SDR_DLLCR4 (DRAMC_IO_BASE + 0x214)
-#define SDR_DQTR0 (DRAMC_IO_BASE + 0x218)
-#define SDR_DQTR1 (DRAMC_IO_BASE + 0x21c)
-#define SDR_DQTR2 (DRAMC_IO_BASE + 0x220)
-#define SDR_DQTR3 (DRAMC_IO_BASE + 0x224)
-#define SDR_DQSTR0 (DRAMC_IO_BASE + 0x228)
-#define SDR_DQSTR1 (DRAMC_IO_BASE + 0x22c)
-#define SDR_CR (DRAMC_IO_BASE + 0x230)
-#define SDR_CFSR (DRAMC_IO_BASE + 0x234)
-#define SDR_0x23c (DRAMC_IO_BASE + 0x23c)
-#define SDR_APR (DRAMC_IO_BASE + 0x240)
-#define SDR_LTR (DRAMC_IO_BASE + 0x244)
-#define SDR_HPCR (DRAMC_IO_BASE + 0x250)
-#define SDR_SCSR (DRAMC_IO_BASE + 0x2e0)
-
-// test-only: is this already the struct? then use it and remove the defines above
struct sunxi_dram_reg {
u32 ccr; /* 0x00 controller configuration register */
u32 dcr; /* 0x04 dram configuration register */
@@ -128,14 +83,14 @@ struct sunxi_dram_reg {
u32 dqstr; /* 0x228 dqs timing register */
u32 dqsbtr; /* 0x22c dqsb timing register */
u32 mcr; /* 0x230 mode configure register */
- u8 res[0xc];
+ u8 res[0x8];
+ u32 reg_23c; /* 0x23c register description unknown!!! */
u32 apr; /* 0x240 arbiter period register */
u32 pldtr; /* 0x244 priority level data threshold reg */
u8 res5[0x8];
u32 hpcr[32]; /* 0x250 host port configure register */
u8 res6[0x10];
u32 csel; /* 0x2e0 controller select register */
-
};

struct dram_para {
--
1.8.0

[Stefan Roese]

From: Stefan Roese <s...@denx.de>

Signed-off-by: Stefan Roese <s...@denx.de>
---

arch/arm/cpu/armv7/sunxi/dram.c | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index ad7c98b..289e814 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -295,19 +295,7 @@ unsigned dramc_get_dram_size(void)
reg_val = readl(SDR_DCR);

chip_den = (reg_val >> 3) & 0x7;

- // test-only: use an algorythm, like dram_size = (32 << chip_den)
- if (chip_den == 0)
- dram_size = 32;
- else if (chip_den == 1)
- dram_size = 64;
- else if (chip_den == 2)
- dram_size = 128;
- else if (chip_den == 3)
- dram_size = 256;
- else if (chip_den == 4)
- dram_size = 512;
- else
- dram_size = 1024;
+ dram_size = min(1024, 32 << chip_den);

if (((reg_val >> 1) & 0x3) == 0x1)
dram_size <<= 1;
--
1.8.0

[Henrik Nordström]

mån 2012-10-29 klockan 17:15 +0100 skrev Stefan Roese:

> From: Stefan Roese <s...@denx.de>
>
> Signed-off-by: Stefan Roese <s...@denx.de>

There an regression here. SPL fails to initialize DRAM after this
change.

Regards
Henrik

[Henrik Nordström]

mån 2012-10-29 klockan 17:15 +0100 skrev Stefan Roese:

> ARM: sunxi: dram.c: Use struct instead of macros to access register

> ARM: sunxi: dram.c: Simplify dramc_set_autorefresh_cycle()

These two have been reverted for now. The first is broken, the second
depends on the first.

Regards
Henrik

[Henrik Nordström]

mån 2012-10-29 klockan 17:15 +0100 skrev Stefan Roese:
>

> @@ -102,15 +113,15 @@ static void mctl_enable_dllx(void)
> }
>
> for (i = 1; i < n; i++)
> - clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x40000000, 0x80000000);
> + clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);
> sdelay(0x100);
>
> for (i = 1; i < n; i++)
> - clrbits_le32(SDR_DLLCR0 + (i << 2), 0xC0000000);
> + clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);
> sdelay(0x1000);
>
> for (i = 1; i < n; i++)
> - clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x80000000, 0x40000000);
> + clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);
> sdelay(0x1000);
> }

There is a copy-paste error here. Better do a search-replace preserving
which bits are toggled.

Regards
Henrik

[stefan...@gmail.com]

From: Stefan Roese <s...@denx.de>

Signed-off-by: Stefan Roese <s...@denx.de>

---
v2:
- Fix copy-paste bug as detected by Henrik

Henrik, this v2 of this patch. Or would you prefer a fixup
patch ontop of the other patches? Just let me know.

arch/arm/cpu/armv7/sunxi/dram.c | 117 +++++++++++++++++++--------------
arch/arm/include/asm/arch-sunxi/dram.h | 49 +-------------

2 files changed, 69 insertions(+), 97 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 53f2ae9..1d1855b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c

@@ -102,15 +113,15 @@ static void mctl_enable_dllx(void)
}

for (i = 1; i < n; i++)
- clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x40000000, 0x80000000);
+ clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000);
sdelay(0x100);

for (i = 1; i < n; i++)
- clrbits_le32(SDR_DLLCR0 + (i << 2), 0xC0000000);

+ clrbits_le32(&dram->dllcr[i], 0xC0000000);

sdelay(0x1000);

for (i = 1; i < n; i++)
- clrsetbits_le32(SDR_DLLCR0 + (i << 2), 0x80000000, 0x40000000);

+ clrsetbits_le32(&dram->dllcr[i], 0x80000000, 0x40000000);

chip_den = (reg_val >> 3) & 0x7;

dram_size = min(1024, 32 << chip_den);

[Alejandro Mery]

Hi,

> @@ -118,11 +129,11 @@ static void mctl_enable_dllx(void)
> #if 0
> static void mctl_disable_dll(void)
> {
> - clrsetbits_le32(SDR_DLLCR0, 0x1 << 30, 0x1U << 31);
> - clrsetbits_le32(SDR_DLLCR1, 0x1 << 30, 0x1U << 31);
> - clrsetbits_le32(SDR_DLLCR2, 0x1 << 30, 0x1U << 31);
> - clrsetbits_le32(SDR_DLLCR3, 0x1 << 30, 0x1U << 31);
> - clrsetbits_le32(SDR_DLLCR4, 0x1 << 30, 0x1U << 31);
> + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)DRAMC_IO_BASE;
> + int i;
> +
> + for (i = 0; i < 5; i++)
> + clrsetbits_le32(&dram->dllcr[i], 0x1 << 30, 0x1U << 31);
> }
> #endif
>

this part conflicts when applied to hno's sunxi-current, the function is
gone. beside that, it boots my cubie =)

regards,
Alejandro Mery

[Stefan Roese]

Yes. As Hernrik reverted 2 patches of my patchset, I thought easiest to
send a v2 of this one patch. It should apply clean when Henrik would
re-apply the reverted "ARM: sunxi: dram.c: Simplify
dramc_set_autorefresh_cycle()".

Or Henrik would re-apply both reverted patches and I could send just the
fix.

Henrik, just let me know if you need a different patch to fix this.

And again sorry for the breakage. All further patches will be tested. No
guarantee for further bugs though! ;)

Thanks,
Stefan

[Henrik Nordström]

tor 2012-11-01 klockan 11:21 +0100 skrev Stefan Roese:

> Yes. As Hernrik reverted 2 patches of my patchset, I thought easiest to
> send a v2 of this one patch. It should apply clean when Henrik would
> re-apply the reverted "ARM: sunxi: dram.c: Simplify
> dramc_set_autorefresh_cycle()".

There was another patch between the two that was not reverted, removing
dead code. But no worries. It's trivial to resolve. No need for a new
version.

> And again sorry for the breakage. All further patches will be tested. No
> guarantee for further bugs though! ;)

No problem.

Regards
Henrik

[Henrik Nordström]

tor 2012-11-01 klockan 10:55 +0100 skrev stefan...@gmail.com:
> From: Stefan Roese <s...@denx.de>
>
> Signed-off-by: Stefan Roese <s...@denx.de>
> ---
> v2:
> - Fix copy-paste bug as detected by Henrik

Applied, after removing the conflicting dead chunk.

Regards
Henrik