[PATCH] Fix sun7i pin assignment for IRQ's

[hp197]

IRQ pins are now according this page: http://linux-sunxi.org/A20/PIO

Signed-off-by: hp197 <he...@nitronetworks.nl>
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 14 --------------
1 file changed, 14 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..4db5e19 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -344,25 +344,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,55 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0

[hp197]

Op zaterdag 20 februari 2016 22:28:35 UTC+1 schreef hp197:

IRQ pins are now according this page: http://linux-sunxi.org/A20/PIO

Signed-off-by: hp197 <he...@nitronetworks.nl>
---
 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..4db5e19 100644

NAK, v2 incomming

[hp197]

After testing IRQ pins we found some bugs in the pinctrl declaration.

Signed-off-by: hp197 <he...@nitronetworks.nl>
---

Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.

Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 25 +++++++++++--------------
1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..0fe173e 100644

@@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {

SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */

+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */

+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */

+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */

+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */

+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */

+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */

+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */

+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
+ /* EINT29 might not work - more testing needed */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */

+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */

+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */

[Chen-Yu Tsai]

On Sun, Feb 21, 2016 at 9:54 AM, hp197 <draak...@gmail.com> wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: hp197 <he...@nitronetworks.nl>

Please resend with your full name on the commit and the SoB.
The patch itself looks good.

ChenYu

[Henry Paulissen]

After testing IRQ pins we found some bugs in the pinctrl declaration.

Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

---

Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.

Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.

Changes in v3:
Changed name from nickname to realname in email and SoB.

[Maxime Ripard]

Hi,

On Sun, Feb 21, 2016 at 02:20:41PM +0100, Henry Paulissen wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.

Your commit log is going to need some work. Which bugs? What tests did
you make? Why are you making these changes while the datasheet says
otherwise?

> Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>
> ---
>
> Changes in v2:
> After some more testing we found irq on PI pins.
> they where on mux6 so this is included in my patch.
>
> Also included is a warning for PI17, this pin was not working
> on apritzel his bPI and he thinks it might be correlated to
> GIC and IRQ 29.
>
> Changes in v3:
> Changed name from nickname to realname in email and SoB.
> ---
> drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 25 +++++++++++--------------
> 1 file changed, 11 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> index cf1ce0c..0fe173e 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> @@ -344,25 +344,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
> SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
> - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */

Have you tried to compile it?

Thanks,
Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[Henry Paulissen]

Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:

Your commit log is going to need some work. Which bugs? What tests did
you make? Why are you making these changes while the datasheet says
otherwise?

Its a fix for a not yet existing bug. I was fiddling around with IRQ's and couldn't get them to work.
I took a dumpster dive into it and found a shitload of contradicting manuals and datasheets.


Take for example the A20 user manual:
http://dl.linux-sunxi.org/A20/A20%20user%20manual%20v1.3%2020141010.pdf

(pin PI14)
Page 237: EINT26 is on mux *5* in the pin overview.
Page 288: EINT26 is on mux *6* in the registers.
 
Page 233: EINT12 is on pin PC19 mux6 in the pin overview.
Page 236: EINT12 is on pin PH12 mux6 in the pin overview.
Page 253: EINT12 is *not* on pin PC19 on the registers.
Page 281: EINT12 is on pin PH12 mux6 in the registers.

So manual may say otherwise, but I hope I have proven that the manual isn't to be trusted.

My patch is based onto testing from both me and Andre (apritzel).
He with a Banana PI M1 and me with a Cubietruck (both A20 soc).

We did a basic test by connecting a pulsing signal to a port and configure kernel to use irq.

e.g.
echo pin# > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio#/direction
echo rising > /sys/class/gpio/gpio#/edge

and check on /proc/interrupts to see if a irq was attached and if it was receiving.

Im not sure what andre his pulse source was, but mine was a 1pps coming from a gps.

Have you tried to compile it?

Yes, otherwise we could have never confirmed that the irq's where on mux6 for the PI ports.

Regards,
Henry

[Julian Calaby]

Hi Henry,

I think Maxime is referring to the fact that your patch removes two
closing parenthesis when one would expect that you'd only remove one.

You have compiled the kernel with this patch applied and no other
modifications, right?

Thanks,

--
Julian Calaby

Email: julian...@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/

[Henry Paulissen]

Op zondag 21 februari 2016 22:55:31 UTC+1 schreef Julian Calaby:

I think Maxime is referring to the fact that your patch removes two
closing parenthesis when one would expect that you'd only remove one.

You have compiled the kernel with this patch applied and no other
modifications, right?
 

Hmm, I see your (and Maxime his) point.
I guess the C bank changes made it into the diff after testing the build.

For what its worth, I corrected and completely checked the new upcoming diff.
My apologies.

Regards,
Henry Paulissen

[Henry Paulissen]

After testing IRQ pins we found some bugs in the pinctrl declaration.

Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>
---

Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.

Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.

Changes in v3:
Changed name from nickname to realname in email and SoB.

Changes in v4:
Added closing parenthesis for the C pins

---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++-----------------
1 file changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..ca7b9a3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),

SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */

- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */

- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */

+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */

SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),

SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */

- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */

+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */

SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),

SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */

- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */

+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */

SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),

SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */

- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */

+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */

SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),

@@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),

[Chen-Yu Tsai]

On Sun, Feb 21, 2016 at 3:17 PM, Henry Paulissen <draak...@gmail.com> wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

Acked-by: Chen-Yu Tsai <we...@csie.org>

[Krzysztof Adamski]

That's quite clear to anybody reading this mailinglist but it won't be
to anyone reading just commit message (and there will be many of them).
You should try to put some of this into the commit message.

[Henry Paulissen]

After testing IRQ pins we found some bugs in the pinctrl declaration.

Both PI* and PC* pins didn't work. PI* pins seemed to be connected
to the wrong mux and PC* pins waren't working at all.

Please note that the A20 soc manual is contradicting between version
and even within the same document for both the PI and PC pins.

Patch is based on testing with the hardware itself.

Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

---

Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.

Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.

Changes in v3:
Changed name from nickname to realname in email and SoB.

Changes in v4:

Added closing parenthesis for the C pins.

Changes in v5:
Added a more detailed description.

[Andre Przywara]

Hi Henry,

On 22/02/16 08:20, Henry Paulissen wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
> Both PI* and PC* pins didn't work. PI* pins seemed to be connected
> to the wrong mux and PC* pins waren't working at all.
>
> Please note that the A20 soc manual is contradicting between version
> and even within the same document for both the PI and PC pins.
>
> Patch is based on testing with the hardware itself.

So I tested this on the BananaPi M1:
None of the PIxx interrupts worked before, but now with this patch on
top of 4.5-rc5 all PI pins accessible on CON3 (expect PI3, which does
not provide an EINT) trigger interrupts as expected.
Also PH0, PH1, PH2, PH20 and PH21 trigger interrupts (as before).
I cannot say anything about the PC ports, because neither PC19-PC22 nor
PH12-PH15 are on a header on the BPi, but now the mapping:
PH0-PH21: EINT0-EINT21, PI10-PI19: EINT22-EINT31
looks reasonable enough to me.

Also PI17 now worked in my latest testing, so not sure if that was a
hiccup at my test setup or the different kernel base I used at the weekend.

So dear committer, feel free to drop the comment there.

> Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

Tested-by: Andre Przywara <andre.p...@arm.com>
Reviewed-by: Andre Przywara <andre.p...@arm.com>

Cheers,
Andre.

[Henry Paulissen]

After testing IRQ pins we found some bugs in the pinctrl declaration.
Both PI* and PC* pins didn't work. PI* pins seemed to be connected
to the wrong mux and PC* pins waren't working at all.

Please note that the A20 soc manual is contradicting between version
and even within the same document for both the PI and PC pins.

Patch is based on testing with the hardware itself.

Tested-by: Andre Przywara <andre.p...@arm.com>
Reviewed-by: Andre Przywara <andre.p...@arm.com>

Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

---

Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.

Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.

Changes in v3:
Changed name from nickname to realname in email and SoB.

Changes in v4:
Added closing parenthesis for the C pins.

Changes in v5:
Added a more detailed description.

Changes in v6:
Removed extra comment about pin I17 (extra tests needed).
Added tested and reviewed by tags.

---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 32 ++++++++++++++-----------------
1 file changed, 14 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..435ad30 100644

@@ -960,65 +956,65 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {

SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),

--
2.5.0

[Maxime Ripard]

Hi,

Usually, the patch title should be prefixed by the subsystem it
applies to so that maintainer and reviewers can spot it more
easily. In this case, it would be something like

pinctrl: sunxi: Fix sun7i pin assignment for IRQ's

On Mon, Feb 22, 2016 at 06:14:07PM +0100, Henry Paulissen wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
> Both PI* and PC* pins didn't work. PI* pins seemed to be connected
> to the wrong mux and PC* pins waren't working at all.
>
> Please note that the A20 soc manual is contradicting between version
> and even within the same document for both the PI and PC pins.

Which sections are in contradiction?

> Patch is based on testing with the hardware itself.

How did you test it? Using the sysfs API, or did you have any hardware
connected to it?

Thanks!

[Linus Walleij]

On Mon, Feb 22, 2016 at 12:17 AM, Henry Paulissen <draak...@gmail.com> wrote:

> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

This v4 patch applied with Chen-Yu's ACK.

Yours,
Linus Walleij

[Linus Walleij]

On Mon, Feb 22, 2016 at 9:20 AM, Henry Paulissen <draak...@gmail.com> wrote:

> After testing IRQ pins we found some bugs in the pinctrl declaration.
> Both PI* and PC* pins didn't work. PI* pins seemed to be connected
> to the wrong mux and PC* pins waren't working at all.
>
> Please note that the A20 soc manual is contradicting between version
> and even within the same document for both the PI and PC pins.
>
> Patch is based on testing with the hardware itself.
>
> Signed-off-by: Henry Paulissen <he...@nitronetworks.nl>

(...)

> Changes in v5:
> Added a more detailed description.

Aha there is a v5. I took out the v4 and applied this
instead.

Yours,
Linus Walleij

[Henry Paulissen]

Op donderdag 25 februari 2016 10:36:38 UTC+1 schreef Linus Walleij:

Aha there is a v5. I took out the v4 and applied this
instead.

There is also a v6.

[Linus Walleij]

On Thu, Feb 25, 2016 at 1:54 AM, Maxime Ripard
<maxime...@free-electrons.com> wrote:
>
> Usually, the patch title should be prefixed by the subsystem it
> applies to so that maintainer and reviewers can spot it more
> easily. In this case, it would be something like
>
> pinctrl: sunxi: Fix sun7i pin assignment for IRQ's
>
> On Mon, Feb 22, 2016 at 06:14:07PM +0100, Henry Paulissen wrote:
>> After testing IRQ pins we found some bugs in the pinctrl declaration.
>> Both PI* and PC* pins didn't work. PI* pins seemed to be connected
>> to the wrong mux and PC* pins waren't working at all.
>>
>> Please note that the A20 soc manual is contradicting between version
>> and even within the same document for both the PI and PC pins.
>
> Which sections are in contradiction?
>
>> Patch is based on testing with the hardware itself.
>
> How did you test it? Using the sysfs API, or did you have any hardware
> connected to it?

I'm taking this patch out of my tree now following Maxime's comments.

I'm a bit annoyed that it is iterating too quickly as well, I will
wait and see for a while.

Yours,
Linus Walleij

[Henry Paulissen]

Op donderdag 25 februari 2016 15:16:49 UTC+1 schreef Linus Walleij:

I'm taking this patch out of my tree now following Maxime's comments.

I'm a bit annoyed that it is iterating too quickly as well, I will
wait and see for a while.

 

All of Maxime his questions where already answered in a reply to him at:
Date: Sun, 21 Feb 2016 11:27:46 -0800 (PST)

Patch V6 is the latest and final.
Code itself is reviewed and tested and the last few iterations where only cosmetic (changing description, etc).

Regards,
Henry

[Maxime Ripard]

Hi,

On Thu, Feb 25, 2016 at 06:26:22AM -0800, Henry Paulissen wrote:
>
>
> Op donderdag 25 februari 2016 15:16:49 UTC+1 schreef Linus Walleij:
>
> >
> > I'm taking this patch out of my tree now following Maxime's comments.
> >
> > I'm a bit annoyed that it is iterating too quickly as well, I will
> > wait and see for a while.
> >
> >
> All of Maxime his questions where already answered in a reply to him at:
> Date: Sun, 21 Feb 2016 11:27:46 -0800 (PST)

And I was not among the recipients of that mail, please try to keep
everyone in Cc.

Commenting on it right now....

[Maxime Ripard]

Hi,

On Sun, Feb 21, 2016 at 11:27:46AM -0800, Henry Paulissen wrote:
>

> Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:
>
> >
> > Your commit log is going to need some work. Which bugs? What tests did
> > you make? Why are you making these changes while the datasheet says
> > otherwise?
> >
>
> Its a fix for a not yet existing bug. I was fiddling around with IRQ's and
> couldn't get them to work.
> I took a dumpster dive into it and found a shitload of contradicting
> manuals and datasheets.
>
>
> Take for example the A20 user manual:
> http://dl.linux-sunxi.org/A20/A20%20user%20manual%20v1.3%2020141010.pdf
>
> (pin PI14)
> Page 237: EINT26 is on mux *5* in the pin overview.
> Page 288: EINT26 is on mux *6* in the registers.
>
> Page 233: EINT12 is on pin PC19 mux6 in the pin overview.
> Page 236: EINT12 is on pin PH12 mux6 in the pin overview.
> Page 253: EINT12 is *not* on pin PC19 on the registers.
> Page 281: EINT12 is on pin PH12 mux6 in the registers.

Ok, so i guess you're actually fixing two different things: the first
one is that some interrupts are using the wrong function, while some
others are just not there at all. It would be great if you could make
two different patches for these.

I guess we could also change SUNXI_FUNCTION_IRQ to enforce the mux
value 6, since you're removing the last users of a different value,
but that can be done as a followup

> So manual may say otherwise, but I hope I have proven that the manual isn't
> to be trusted.
>
> My patch is based onto testing from both me and Andre (apritzel).
> He with a Banana PI M1 and me with a Cubietruck (both A20 soc).
>
> We did a basic test by connecting a pulsing signal to a port and configure
> kernel to use irq.
>
> e.g.
> echo pin# > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio#/direction
> echo rising > /sys/class/gpio/gpio#/edge
>
> and check on /proc/interrupts to see if a irq was attached and if it was
> receiving.
>
> Im not sure what andre his pulse source was, but mine was a 1pps coming
> from a gps.

That's a great explanation overall, it should just be in the commit
log itself. A git commit is easy to find, the discussion that was
triggered by it not so much.

Thanks!

[Linus Walleij]

Sigh this is too high iteration rate for me. At this point any changes need
to come as patches on top of v5.

Yours,
Linus Walleij