[PATCH 46/50] arm64: Add dsb around EL2 TLB flush

[Jan Kiszka]

This adds the barriers needed according to ARM DDI 0487A.j, K10.5.3.

Without them, frequent crashes can be observed on the Hi6220, e.g. on
the first access of the freshly mapped GICD.

Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
---
hypervisor/arch/arm64/include/asm/paging.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hypervisor/arch/arm64/include/asm/paging.h b/hypervisor/arch/arm64/include/asm/paging.h
index 2d17acd..03bae3a 100644
--- a/hypervisor/arch/arm64/include/asm/paging.h
+++ b/hypervisor/arch/arm64/include/asm/paging.h
@@ -258,8 +258,12 @@ static inline void arm_paging_vcpu_flush_tlbs(void)
/* Only executed on hypervisor paging struct changes */
static inline void arch_paging_flush_page_tlbs(unsigned long page_addr)
{
- asm volatile("tlbi vae2, %0\n"
- : : "r" (page_addr >> PAGE_SHIFT));
+ asm volatile(
+ "dsb ish\n\t"
+ "tlbi vae2, %0\n\t"
+ "dsb ish\n\t"
+ "isb\n\t"
+ : : "r" (page_addr >> PAGE_SHIFT));
}

/* Used to clean the PAGE_MAP_COHERENT page table changes */
--
2.1.4