[PATCH 12/21] arm, configs: Move content of platform.h into system configuration

[Jan Kiszka]

Overcome the constantly growing ugly platform.h by defining
platform_info.arm in the system configuration. We need the base
addresses of GICD/C/H/V/R here and the maintenance interrupt number. No
need to account for the fact that only GICv3 needs GICR and not C/H/V -
makes the definition more compact, and we have enough space.

Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
---
configs/bananapi.c | 7 +++
configs/jetson-tk1.c | 7 +++
configs/vexpress.c | 12 ++++++
hypervisor/arch/arm/control.c | 3 +-
hypervisor/arch/arm/dbg-write.c | 1 -
hypervisor/arch/arm/gic-common.c | 1 -
hypervisor/arch/arm/gic-v2.c | 25 ++++++-----
hypervisor/arch/arm/gic-v3.c | 16 +++----
hypervisor/arch/arm/include/asm/platform.h | 69 ------------------------------
hypervisor/arch/arm/irqchip.c | 9 ++--
hypervisor/arch/arm/traps.c | 1 -
hypervisor/include/jailhouse/cell-config.h | 9 ++++
12 files changed, 61 insertions(+), 99 deletions(-)
delete mode 100644 hypervisor/arch/arm/include/asm/platform.h

diff --git a/configs/bananapi.c b/configs/bananapi.c
index b45604b..6f1103f 100644
--- a/configs/bananapi.c
+++ b/configs/bananapi.c
@@ -34,6 +34,13 @@ struct {
.size = 0x1000,
.flags = JAILHOUSE_MEM_IO,
},
+ .platform_info.arm = {
+ .gicd_base = 0x01c81000,
+ .gicc_base = 0x01c82000,
+ .gich_base = 0x01c84000,
+ .gicv_base = 0x01c86000,
+ .maintenance_irq = 25,
+ },
.root_cell = {
.name = "Banana-Pi",

diff --git a/configs/jetson-tk1.c b/configs/jetson-tk1.c
index 5691223..36bebcb 100644
--- a/configs/jetson-tk1.c
+++ b/configs/jetson-tk1.c
@@ -37,6 +37,13 @@ struct {
.size = 0x1000,
.flags = JAILHOUSE_MEM_IO,
},
+ .platform_info.arm = {
+ .gicd_base = 0x50041000,
+ .gicc_base = 0x50042000,
+ .gich_base = 0x50044000,
+ .gicv_base = 0x50046000,
+ .maintenance_irq = 25,
+ },
.root_cell = {
.name = "Jetson-TK1",

diff --git a/configs/vexpress.c b/configs/vexpress.c
index 663f84a..319bb58 100644
--- a/configs/vexpress.c
+++ b/configs/vexpress.c
@@ -32,6 +32,18 @@ struct {
.size = 0x1000,
.flags = JAILHOUSE_MEM_IO,
},
+ .platform_info.arm = {
+#ifdef CONFIG_ARM_GIC_V3
+ .gicd_base = 0x2f000000,
+ .gicr_base = 0x2f100000,
+#else /* GICv2 */
+ .gicd_base = 0x2c001000,
+ .gicc_base = 0x2c002000,
+ .gich_base = 0x2c004000,
+ .gicv_base = 0x2c006000,
+#endif
+ .maintenance_irq = 25,
+ },
.root_cell = {
.name = "VExpress Linux",

diff --git a/hypervisor/arch/arm/control.c b/hypervisor/arch/arm/control.c
index 17ba172..0ad05a2 100644
--- a/hypervisor/arch/arm/control.c
+++ b/hypervisor/arch/arm/control.c
@@ -18,7 +18,6 @@
#include <jailhouse/string.h>
#include <asm/control.h>
#include <asm/irqchip.h>
-#include <asm/platform.h>
#include <asm/processor.h>
#include <asm/smp.h>
#include <asm/sysregs.h>
@@ -336,7 +335,7 @@ unsigned int arm_cpu_virt2phys(struct cell *cell, unsigned int virt_id)
bool arch_handle_phys_irq(struct per_cpu *cpu_data, u32 irqn,
unsigned int count_event)
{
- if (irqn == MAINTENANCE_IRQ) {
+ if (irqn == system_config->platform_info.arm.maintenance_irq) {
cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MAINTENANCE] +=
count_event;
irqchip_inject_pending(cpu_data);
diff --git a/hypervisor/arch/arm/dbg-write.c b/hypervisor/arch/arm/dbg-write.c
index dc3989f..076821b 100644
--- a/hypervisor/arch/arm/dbg-write.c
+++ b/hypervisor/arch/arm/dbg-write.c
@@ -14,7 +14,6 @@
#include <jailhouse/printk.h>
#include <jailhouse/processor.h>
#include <asm/debug.h>
-#include <asm/platform.h>

static struct uart_chip uart;

diff --git a/hypervisor/arch/arm/gic-common.c b/hypervisor/arch/arm/gic-common.c
index 675c2ee..695604c 100644
--- a/hypervisor/arch/arm/gic-common.c
+++ b/hypervisor/arch/arm/gic-common.c
@@ -18,7 +18,6 @@
#include <asm/gic.h>
#include <asm/irqchip.h>
#include <asm/percpu.h>
-#include <asm/platform.h>
#include <asm/spinlock.h>
#include <asm/traps.h>

diff --git a/hypervisor/arch/arm/gic-v2.c b/hypervisor/arch/arm/gic-v2.c
index 3123322..913e05c 100644
--- a/hypervisor/arch/arm/gic-v2.c
+++ b/hypervisor/arch/arm/gic-v2.c
@@ -14,24 +14,22 @@
#include <jailhouse/mmio.h>
#include <asm/gic.h>
#include <asm/irqchip.h>
-#include <asm/platform.h>
#include <asm/setup.h>

static unsigned int gic_num_lr;

extern void *gicd_base;
void *gicc_base;
-void *gicv_base;
void *gich_base;

static int gic_init(void)
{
int err;

- /* FIXME: parse device tree */
- gicc_base = GICC_BASE;
- gich_base = GICH_BASE;
- gicv_base = GICV_BASE;
+ gicc_base =
+ (void *)(unsigned long)system_config->platform_info.arm.gicc_base;
+ gich_base =
+ (void *)(unsigned long)system_config->platform_info.arm.gich_base;

err = arch_map_device(gicc_base, gicc_base, GICC_SIZE);
if (err)
@@ -56,6 +54,7 @@ static void gic_clear_pending_irqs(void)

static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
{
+ unsigned int mnt_irq = system_config->platform_info.arm.maintenance_irq;
unsigned int i;
bool root_shutdown = is_shutdown && (cpu_data->cell == &root_cell);
u32 active;
@@ -72,8 +71,7 @@ static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
}

/* Ensure all IPIs and the maintenance PPI are enabled */
- mmio_write32(gicd_base + GICD_ISENABLER,
- 0x0000ffff | (1 << MAINTENANCE_IRQ));
+ mmio_write32(gicd_base + GICD_ISENABLER, 0x0000ffff | (1 << mnt_irq));

/*
* Disable PPIs, except for the maintenance interrupt.
@@ -81,8 +79,8 @@ static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
* enabled - except for the maintenance interrupt we used.
*/
mmio_write32(gicd_base + GICD_ICENABLER,
- root_shutdown ? 1 << MAINTENANCE_IRQ :
- 0xffff0000 & ~(1 << MAINTENANCE_IRQ));
+ root_shutdown ? 1 << mnt_irq :
+ 0xffff0000 & ~(1 << mnt_irq));

if (is_shutdown)
mmio_write32(gich_base + GICH_HCR, 0);
@@ -107,12 +105,12 @@ static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)

static int gic_cpu_init(struct per_cpu *cpu_data)
{
+ unsigned int mnt_irq = system_config->platform_info.arm.maintenance_irq;
u32 vtr, vmcr;
u32 cell_gicc_ctlr, cell_gicc_pmr;

/* Ensure all IPIs and the maintenance PPI are enabled. */
- mmio_write32(gicd_base + GICD_ISENABLER,
- 0x0000ffff | (1 << MAINTENANCE_IRQ));
+ mmio_write32(gicd_base + GICD_ISENABLER, 0x0000ffff | (1 << mnt_irq));

cell_gicc_ctlr = mmio_read32(gicc_base + GICC_CTLR);
cell_gicc_pmr = mmio_read32(gicc_base + GICC_PMR);
@@ -183,7 +181,8 @@ static int gic_cell_init(struct cell *cell)
* here.
* As for now, none of them seem to have virtualization extensions.
*/
- err = paging_create(&cell->arch.mm, (unsigned long)gicv_base,
+ err = paging_create(&cell->arch.mm,
+ system_config->platform_info.arm.gicv_base,
GICC_SIZE, (unsigned long)gicc_base,
(PTE_FLAG_VALID | PTE_ACCESS_FLAG |
S2_PTE_ACCESS_RW | S2_PTE_FLAG_DEVICE),
diff --git a/hypervisor/arch/arm/gic-v3.c b/hypervisor/arch/arm/gic-v3.c
index 43d0d1c..1ae6530 100644
--- a/hypervisor/arch/arm/gic-v3.c
+++ b/hypervisor/arch/arm/gic-v3.c
@@ -18,7 +18,6 @@
#include <asm/control.h>
#include <asm/gic.h>
#include <asm/irqchip.h>
-#include <asm/platform.h>
#include <asm/setup.h>
#include <asm/traps.h>

@@ -42,8 +41,8 @@ static int gic_init(void)
if (!(mmio_read32(gicd_base + GICD_CTLR) & GICD_CTLR_ARE_NS))
return trace_error(-EIO);

- /* FIXME: parse a dt */
- gicr_base = GICR_BASE;
+ gicr_base =
+ (void *)(unsigned long)system_config->platform_info.arm.gicr_base;

/* Let the per-cpu code access the redistributors */
return arch_map_device(gicr_base, gicr_base, GICR_SIZE);
@@ -70,6 +69,7 @@ static void gic_clear_pending_irqs(void)

static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
{
+ unsigned int mnt_irq = system_config->platform_info.arm.maintenance_irq;
unsigned int i;
void *gicr = cpu_data->gicr_base;
unsigned long active;
@@ -90,8 +90,7 @@ static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
}

/* Ensure all IPIs and the maintenance PPI are enabled. */
- mmio_write32(gicr + GICR_ISENABLER,
- 0x0000ffff | (1 << MAINTENANCE_IRQ));
+ mmio_write32(gicr + GICR_ISENABLER, 0x0000ffff | (1 << mnt_irq));

/*
* Disable PPIs, except for the maintenance interrupt.
@@ -99,8 +98,8 @@ static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
* enabled - except for the maintenance interrupt we used.
*/
mmio_write32(gicr + GICR_ICENABLER,
- root_shutdown ? 1 << MAINTENANCE_IRQ :
- 0xffff0000 & ~(1 << MAINTENANCE_IRQ));
+ root_shutdown ? 1 << mnt_irq :
+ 0xffff0000 & ~(1 << mnt_irq));

if (root_shutdown) {
/* Restore the root config */
@@ -121,6 +120,7 @@ static void gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)

static int gic_cpu_init(struct per_cpu *cpu_data)
{
+ unsigned int mnt_irq = system_config->platform_info.arm.maintenance_irq;
u64 typer;
u32 pidr;
u32 cell_icc_ctlr, cell_icc_pmr, cell_icc_igrpen1;
@@ -153,7 +153,7 @@ static int gic_cpu_init(struct per_cpu *cpu_data)

/* Ensure all IPIs and the maintenance PPI are enabled. */
mmio_write32(redist_base + GICR_SGI_BASE + GICR_ISENABLER,
- 0x0000ffff | (1 << MAINTENANCE_IRQ));
+ 0x0000ffff | (1 << mnt_irq));

/*
* Set EOIMode to 1
diff --git a/hypervisor/arch/arm/include/asm/platform.h b/hypervisor/arch/arm/include/asm/platform.h
deleted file mode 100644
index 24f74ff..0000000
--- a/hypervisor/arch/arm/include/asm/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Jailhouse, a Linux-based partitioning hypervisor
- *
- * Copyright (c) ARM Limited, 2014
- *
- * Authors:
- * Jean-Philippe Brucker <jean-phili...@arm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef _JAILHOUSE_ASM_PLATFORM_H
-#define _JAILHOUSE_ASM_PLATFORM_H
-
-/*
- * All those things are defined in the device tree. This header *must*
- * disappear. The GIC includes will need to be sanitized in order to avoid ID
- * naming conflicts.
- */
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_MACH_VEXPRESS
-
-# ifdef CONFIG_ARM_GIC_V3
-# define GICD_BASE ((void *)0x2f000000)
-# define GICR_BASE ((void *)0x2f100000)
-
-# else /* GICv2 */
-# define GICD_BASE ((void *)0x2c001000)
-# define GICC_BASE ((void *)0x2c002000)
-/*
- * WARN: most device trees are broken and report only one page for the GICC.
- * It will brake the handle_irq code, since the GICC_DIR register is located at
- * offset 0x1000...
- */
-# define GICH_BASE ((void *)0x2c004000)
-# define GICV_BASE ((void *)0x2c006000)
-
-# endif /* GIC */
-
-# define MAINTENANCE_IRQ 25
-
-#endif /* CONFIG_MACH_VEXPRESS */
-
-#ifdef CONFIG_MACH_SUN7I
-
-# define GICD_BASE ((void *)0x01c81000)
-# define GICC_BASE ((void *)0x01c82000)
-# define GICH_BASE ((void *)0x01c84000)
-# define GICV_BASE ((void *)0x01c86000)
-
-# define MAINTENANCE_IRQ 25
-
-#endif /* CONFIG_MACH_SUN7I */
-
-#ifdef CONFIG_MACH_TEGRA124
-
-# define GICD_BASE ((void *)0x50041000)
-# define GICC_BASE ((void *)0x50042000)
-# define GICH_BASE ((void *)0x50044000)
-# define GICV_BASE ((void *)0x50046000)
-
-# define MAINTENANCE_IRQ 25
-
-#endif /* CONFIG_MACH_TEGRA124 */
-
-#endif /* !__ASSEMBLY__ */
-#endif /* !_JAILHOUSE_ASM_PLATFORM_H */
diff --git a/hypervisor/arch/arm/irqchip.c b/hypervisor/arch/arm/irqchip.c
index 27ae2d3..7c2d754 100644
--- a/hypervisor/arch/arm/irqchip.c
+++ b/hypervisor/arch/arm/irqchip.c
@@ -12,6 +12,7 @@
* the COPYING file in the top-level directory.
*/

+#include <jailhouse/control.h>
#include <jailhouse/entry.h>
#include <jailhouse/mmio.h>
#include <jailhouse/paging.h>
@@ -20,7 +21,6 @@
#include <asm/control.h>
#include <asm/gic.h>
#include <asm/irqchip.h>
-#include <asm/platform.h>
#include <asm/setup.h>
#include <asm/sysregs.h>

@@ -150,6 +150,7 @@ void irqchip_cpu_shutdown(struct per_cpu *cpu_data)

int irqchip_cell_init(struct cell *cell)
{
+ unsigned int mnt_irq = system_config->platform_info.arm.maintenance_irq;
const struct jailhouse_irqchip *chip;
unsigned int n, pos;
int err;
@@ -169,7 +170,7 @@ int irqchip_cell_init(struct cell *cell)
* the hypervisor.
*/
cell->arch.irq_bitmap[0] = ~((1 << SGI_INJECT) | (1 << SGI_EVENT) |
- (1 << MAINTENANCE_IRQ));
+ (1 << mnt_irq));

err = irqchip.cell_init(cell);
if (err)
@@ -238,8 +239,8 @@ int irqchip_init(void)
if (irqchip_is_init)
return 0;

- /* FIXME: parse device tree */
- gicd_base = GICD_BASE;
+ gicd_base =
+ (void *)(unsigned long)system_config->platform_info.arm.gicd_base;

err = arch_map_device(gicd_base, gicd_base, GICD_SIZE);
if (err)
diff --git a/hypervisor/arch/arm/traps.c b/hypervisor/arch/arm/traps.c
index 80e66b1..67b8fd1 100644
--- a/hypervisor/arch/arm/traps.c
+++ b/hypervisor/arch/arm/traps.c
@@ -19,7 +19,6 @@
#include <asm/control.h>
#include <asm/gic.h>
#include <asm/psci.h>
-#include <asm/platform.h>
#include <asm/traps.h>
#include <asm/sysregs.h>

diff --git a/hypervisor/include/jailhouse/cell-config.h b/hypervisor/include/jailhouse/cell-config.h
index a2baaea..e4d6006 100644
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -171,6 +171,15 @@ struct jailhouse_system {
struct jailhouse_iommu
iommu_units[JAILHOUSE_MAX_IOMMU_UNITS];
} __attribute__((packed)) x86;
+ struct {
+ u64 gicd_base;
+ u64 gicc_base;
+ u64 gich_base;
+ u64 gicv_base;
+ u64 gicr_base;
+ u8 maintenance_irq;
+ u8 padding[3];
+ } __attribute__((packed)) arm;
} __attribute__((packed)) platform_info;
__u32 interrupt_limit;
struct jailhouse_cell_desc root_cell;
--
2.1.4