Processor Root Complex outside AMD IOMMU

[Valentine Sinitsyn]

Hi all,

I'm finishing with AMD IOMMU ACPI tables parser, and looks like PCI
device 00:00.0 (processor root complex which is host bridge) is outside
IOMMU. Did anyone experienced anything similar with Intel? And how
should we treat this: as a bug in ACPI table (Linux gives no complaints,
however) or just leave this device alone?

I haven't looked into details, like Linux' amd_iommu driver yet.

Valentine

[Valentine Sinitsyn]

> should we treat this: as a bug in ACPI table (Linux gives no complaints,
> however) or just leave this device alone?

I mean, it looks reasonable that the root complex is not under control
of the IOMMU, so it probably should be skipped, but I see no similar
code in VTD implementation.

Valentine

[Zhangjun (V)]

>I'm finishing with AMD IOMMU ACPI tables parser, and looks like PCI device 00:00.0 (processor root complex which is host bridge) is outside IOMMU. Did anyone experienced anything similar with Intel? And how should we treat this: as a bug in ACPI table (Linux gives no complaints,
>however) or just leave this device alone?

PCI device 00:00.0 is a DMI2 Host Bridge. It is different from other PCIe Port.


-----邮件原件-----
发件人: jailho...@googlegroups.com [mailto:jailho...@googlegroups.com] 代表 Valentine Sinitsyn
发送时间: 2015年2月13日 15:14
收件人: jailho...@googlegroups.com
主题: Processor Root Complex outside AMD IOMMU

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[Valentine Sinitsyn]

Hi Zhangjun,

Thanks for replying.

> PCI device 00:00.0 is a DMI2 Host Bridge. It is different from other PCIe Port.

I understand it's different. However I was surprised a bit there seems
to be no special handling for it in VT-d code, and I wanted to know why
it isn't required in Intel case.

Valentine

[Jan Kiszka]

There is no need for any special handling. In the worst case, we list a
device in the tables that will never generate a transaction visible to
an IOMMU.

Jan

--
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[Valentine Sinitsyn]

On 17.02.2015 00:05, Jan Kiszka wrote:
> There is no need for any special handling. In the worst case, we list a
> device in the tables that will never generate a transaction visible to
> an IOMMU.

Hmm. On jailhouse-config-create AMD port, I simply get an exception
saying the device is outside scope of the IOMMU (which is of course true
as root complex is not in IVRS tables, and it probably shouldn't be).
How do you handle this with VT-d?

Valentine

[Jan Kiszka]

AH, that safety check.

Well, on Intel, we usually have one DMAR unit with the "catch all" flag
set, i.e. one that covers all remaining devices in a segment. That
includes the host bridge. If AMD ACPI tables look different, we will
have to add an exception to the check.

[Valentine Sinitsyn]

On 17.02.2015 01:11, Jan Kiszka wrote:
> Well, on Intel, we usually have one DMAR unit with the "catch all" flag
> set, i.e. one that covers all remaining devices in a segment. That

I guess it's also the reason why you don't have complaints on IOMMU
being outside IOMMU itself on Intel (I just got one such exception)?

Okay, I'll change that safety check to skip root complex and IOMMU device.

Valentine

[Jan Kiszka]

On 2015-02-17 11:35, Valentine Sinitsyn wrote:
> On 17.02.2015 01:11, Jan Kiszka wrote:
>> Well, on Intel, we usually have one DMAR unit with the "catch all" flag
>> set, i.e. one that covers all remaining devices in a segment. That
> I guess it's also the reason why you don't have complaints on IOMMU
> being outside IOMMU itself on Intel (I just got one such exception)?

On Intel, the IOMMUs are not listed as PCI devices, like on AMD.

>
> Okay, I'll change that safety check to skip root complex and IOMMU device.

Ack.