Six level page tables

[Valentine Sinitsyn]

Hi everybody,

Currently, Jailhouse defines MAX_PAGE_TABLES as 4 on x86, which is fairy
enough for any x86 CPU in existence. However, page table handling code
(hypervisor/paging.c) is used both from CPU-related and IOMMU-related
code (e.g. vmx.c and vtd.c).

The tricky part is AMD IOMMU page tables are really 6-level. Although we
don't need that much, having all six levels could be useful if we were
to share page tables between CPU and IOMMU in the future.

However, if I create six-level paging structures (see [1], for
instance), I got random bugs suggesting the page tables are not filled
properly. Surely, I can trim AMD IOMMU page tables back to 4 levels (and
probably will do just that, at least in the first release), but the
question is: what can break handling both 4-level (for CPU) and 6-levels
paging structs in hypervisor/paging.c simultaneously? I did a quick look
at the code, but didn't have much time to investigate it properly.
MAX_PAGE_TABLES is used only in paging_destroy() and shouldn't have any
issues, everything else seems to be generic enough.

Thanks,
Valentine

[1]
https://github.com/vsinitsyn/jailhouse/blob/amd-vi/hypervisor/arch/x86/amd_iommu_paging.c

[Jan Kiszka]

paging_destroy can be called from paging_create when breaking up a
larger page. Not sure, though, if that happens while you are setting up
your structures. But as that is trivial to adjust, I'd give it a try.

Jan

--
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[Valentine Sinitsyn]

Hi,


Pardon for resurrecting an old thread.

Not as trivial, though. arch_paging_init() also implies
MAX_PAGE_TABLE_LEVELS will be set to four, at least for x86. This won't
probably be to hard to trace everything and make it work with 6-level
page tables correctly, but as there is not much practical sense in it,
I'd stick to 4 level ones now. Linux does the same btw

Valentine