[siemens/jailhouse] 314922: inmates/lib: cmdline.c
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GitHub
17 lip 2016, 13:13:5517.07.2016
do jailho...@googlegroups.com
Branch: refs/heads/master
Home: https://github.com/siemens/jailhouse
Commit: 314922e8bb720d917e44906600a29ef6185b74ac
https://github.com/siemens/jailhouse/commit/314922e8bb720d917e44906600a29ef6185b74ac
Author: Xuguo Wang <hudd...@gmail.com>
Date: 2016-05-31 (Tue, 31 May 2016)
Changed paths:
M inmates/lib/cmdline.c
Log Message:
-----------
inmates/lib: cmdline.c
There is no point in checking for *p == 0 in the while loop,
after over the blanks, then checking for the parameters, if
find, return true, otherwise continue check the parameters,
if to the end of the cmdline, return false.
Signed-off-by: Xuguo Wang <hudd...@gmail.com>
[Jan: also removed curly braces]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 3cfdd3aba4bb9a91bef54298522812ffcc22b3af
https://github.com/siemens/jailhouse/commit/3cfdd3aba4bb9a91bef54298522812ffcc22b3af
Author: Ralf Ramsauer <ra...@ramses-pyramidenbau.de>
Date: 2016-06-13 (Mon, 13 Jun 2016)
Changed paths:
M tools/jailhouse-config-create
Log Message:
-----------
tools: simplify python statement
Signed-off-by: Ralf Ramsauer <ra...@ramses-pyramidenbau.de>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: fe6decf9d3b9a4fd8412f2dbc0d939b965dcc073
https://github.com/siemens/jailhouse/commit/fe6decf9d3b9a4fd8412f2dbc0d939b965dcc073
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-13 (Mon, 13 Jun 2016)
Changed paths:
M hypervisor/arch/x86/amd_iommu.c
M hypervisor/arch/x86/include/asm/amd_iommu.h
Log Message:
-----------
x86: Add missing include to amd_iommu.h
Reported by header-check script: We need this in the header due to the
use of struct jailhouse_memory. Consequently, we can remove the include
from the corresponding amd_iommu.c.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6b7bef821e30d07f3a922c60ba34da623b2a0b31
https://github.com/siemens/jailhouse/commit/6b7bef821e30d07f3a922c60ba34da623b2a0b31
Author: cyng93 <cyn...@gmail.com>
Date: 2016-06-15 (Wed, 15 Jun 2016)
Changed paths:
A Documentation/setup-on-banana-pi-arm-board.md
M README.md
Log Message:
-----------
Documentation: Move BananaPi-related docs out
This patch move BananaPi-related documentation out from `README.md` to
`Documentation/setup-on-banana-pi-arm-board.md`
Signed-off-by: CHING-YI NG <cyn...@gmail.com>
[Jan: removed some blank lines from README.md]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 60121418e65109e6280d6aa591d6558b66dab70b
https://github.com/siemens/jailhouse/commit/60121418e65109e6280d6aa591d6558b66dab70b
Author: cyng93 <cyn...@gmail.com>
Date: 2016-06-15 (Wed, 15 Jun 2016)
Changed paths:
M Documentation/setup-on-banana-pi-arm-board.md
Log Message:
-----------
Documentation: More BananaPi documentation
This patch include more details about how to setup Jailhouse on a BananaPi-M1 board.
Basically this documentation covered:
1. Installation of Bananian(BananaPi offical OS) on BananaPi
2. Modifying U-boot configuration on BananaPi to run Jailhouse.
3. Update Bananian to newer kernel so Jailhouse could works.
- Compiling Kernel.
- Installing Kernel.
4. Installing Jailhouse on BananaPi.
5. Simple demo/test: Running Jailhouse with Freertos-cell on BananaPi.
Signed-off-by: CHING-YI NG <cyn...@gmail.com>
[Jan: removed external media link showing FUSE selection - not needed]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: a9f949b08350538dd52d28c4477f4fcb902b3848
https://github.com/siemens/jailhouse/commit/a9f949b08350538dd52d28c4477f4fcb902b3848
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-15 (Wed, 15 Jun 2016)
Changed paths:
M Documentation/setup-on-banana-pi-arm-board.md
Log Message:
-----------
Documentation: Rewrap Banana Pi README to 80 chars
For better readability in the absence of a markdown viewer.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: da353b5769a2a2266f206c1d0e53402e4b99386c
https://github.com/siemens/jailhouse/commit/da353b5769a2a2266f206c1d0e53402e4b99386c
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/asm-defines.c
M hypervisor/arch/arm/entry.S
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/setup.c
Log Message:
-----------
arm: Use asm-defines.h for struct per_cpu members
Port the logic over from x86 and also drop CHECK_ASSUMPTION here.
The only slightly ugly detail: the PERCPU_SIZE_SHIFT define is now
duplicated in both asm/percpu.h instances because there is no good
generic header yet to hold it. Can be cleaned up later on.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: fd447ceecb0e2555d017c3b73c9bd5d9b62f1436
https://github.com/siemens/jailhouse/commit/fd447ceecb0e2555d017c3b73c9bd5d9b62f1436
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/smp-vexpress.c
Log Message:
-----------
arm: Add missing printk.h include
Some implicit inclusion disappeared.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 7c2644bf2bd841b5d97a8f94856eb57b753a2ef9
https://github.com/siemens/jailhouse/commit/7c2644bf2bd841b5d97a8f94856eb57b753a2ef9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Fix build warning in gic-v3
Leftover from the mmio_perform_access refactoring.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 315273ebcf6d3cc2c28bc3744118fb2f66a72a54
https://github.com/siemens/jailhouse/commit/315273ebcf6d3cc2c28bc3744118fb2f66a72a54
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
arm: Remove unneeded include from irqchip.h
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 0e82670826fd2283d7eb032a3eb11ccf8013c815
https://github.com/siemens/jailhouse/commit/0e82670826fd2283d7eb032a3eb11ccf8013c815
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Un-inline spi_in_cell
To big to be inlined, and we also want to avoid dereferencing struct
cell in the header due to upcoming include reordering.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 03475882880dc5ae49d0852c628a8b8958be80ac
https://github.com/siemens/jailhouse/commit/03475882880dc5ae49d0852c628a8b8958be80ac
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove write-only priority field from pending_irq
We do not support interrupt priorities so far, and we may have to model
them differently into queues once we do. Remove the de facto unused
field.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 3b6a758cb690553583fab3156bce14114775e726
https://github.com/siemens/jailhouse/commit/3b6a758cb690553583fab3156bce14114775e726
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove maintenance flag from pending_irq.type.sgi
It was always cleared.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d62540a7a2a5a6c769550bd250c359bea3910795
https://github.com/siemens/jailhouse/commit/d62540a7a2a5a6c769550bd250c359bea3910795
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove hw flag from pending_irq
Can be derived from virt_id.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 05c1d67e0a7913f967a49a76de8cf93dafba1489
https://github.com/siemens/jailhouse/commit/05c1d67e0a7913f967a49a76de8cf93dafba1489
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove cpuid from pending_irq
Was always set to 0.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 35a46c75c5eb577c9c780340cdbc92d844d1eaca
https://github.com/siemens/jailhouse/commit/35a46c75c5eb577c9c780340cdbc92d844d1eaca
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove irq field from pending_irq
Always identical to virt_id.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b77b9793126fd278ec3839cbead5bf21a389bdd0
https://github.com/siemens/jailhouse/commit/b77b9793126fd278ec3839cbead5bf21a389bdd0
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove return code from irqchip_inject_pending
It's always 0.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f5dcc13bcf89d190d35b99cf79a8586ea7c1a93d
https://github.com/siemens/jailhouse/commit/f5dcc13bcf89d190d35b99cf79a8586ea7c1a93d
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove unused return code of irqchip_set_pending
No caller evaluated it so far, and none of them has a use case for it.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 35b1928d4977040a4a9f4fc1f2a093882182a953
https://github.com/siemens/jailhouse/commit/35b1928d4977040a4a9f4fc1f2a093882182a953
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Disable maintenance interrupt on successful injection
We enable the maintenance interrupt when all list registers are in use.
However, there was no disabling of it again. Apparently, it rarely
triggered in the field, otherwise we would have seen a lot of
maintenance interrupt storms, thus locked-up systems.
This introduces another callback to enable or disable the maintenance
interrupt. It is now controlled by irqchip_inject_pending, the function
that is also called when handling a maintenance interrupt.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 9fc9f67f05c9fbe872f647a0d47f54e7dbb9b90f
https://github.com/siemens/jailhouse/commit/9fc9f67f05c9fbe872f647a0d47f54e7dbb9b90f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Make sure to not queue interrupt that were rejected as duplicates
If the inject_irq callback detect that an interrupt is already queued
in some list register, do not insert it into the software queue, thus
coalesce the event like real hardware does.
The change in the return code of inject_irq is more cosmetic, to reflect
the meaning better.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8b121b498b6e2f204c9b128b42e5423118be220b
https://github.com/siemens/jailhouse/commit/8b121b498b6e2f204c9b128b42e5423118be220b
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Convert software queue of pending interrupts into a ring
This massively simplifies the code and reduces the memory usage in
struct per_cpu. However, adding interrupt priorities later on may
require another rework.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: c8a9a6f84885c366160a394aaaf08715e426eaf4
https://github.com/siemens/jailhouse/commit/c8a9a6f84885c366160a394aaaf08715e426eaf4
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove try_inject parameter from irqchip_set_pending
We can only perform injection (and we also always want to) if target
CPU equals caller CPU, and this is better checked inside the function.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: e24bab3f5e70d877d470659569f22e2838813d0f
https://github.com/siemens/jailhouse/commit/e24bab3f5e70d877d470659569f22e2838813d0f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Enable maintenance interrupt also from irqchip_set_pending
In case we set an interrupt pending for the local CPU and cannot queue
it with the hardware, make sure the maintenance interrupt is on.
Otherwise, we risk to delay guest interrupts or cause the guest to get
stuck.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6f28047e0f4d78af4a712e6f1f2824e9a030a888
https://github.com/siemens/jailhouse/commit/6f28047e0f4d78af4a712e6f1f2824e9a030a888
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Enable / disable maintenance interrupt in distributor
We did not get any maintenance interrupts so far because we didn't
enable the source in the distributor so far. Fix this, but also disable
it again when shutting down.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8bf054eec255f83dcb98960f8de2508ff4a1d92d
https://github.com/siemens/jailhouse/commit/8bf054eec255f83dcb98960f8de2508ff4a1d92d
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Protect hypervisor used SGIs and PPIs from cell changes
We must not allow the cells to manipulate distributor registers or
register bits related to the hypervisor SGIs or the maintenance
interrupt.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 313bfa1a1f9b126dcbbe467ac60f1f35c6a82c61
https://github.com/siemens/jailhouse/commit/313bfa1a1f9b126dcbbe467ac60f1f35c6a82c61
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Make cpu_init and cpu_reset callbacks mandatory
No need for checking them to be NULL, we need them in both
implementations.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f4aa33bef18a6a17069f46915b92ea935e78b107
https://github.com/siemens/jailhouse/commit/f4aa33bef18a6a17069f46915b92ea935e78b107
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Reject unknown GIC versions
We would likely crash anyway due to irqchip containing only NULL
pointers.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6e68f512b1cb75c3b07feb898eea17f032ec1378
https://github.com/siemens/jailhouse/commit/6e68f512b1cb75c3b07feb898eea17f032ec1378
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Consolidate gic_irqchip to irqchip
Likely, we will never support alternative irqchips to the GIC (only
cascaded ones). So this copying-over is not required.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8384f472bc9f509b2c0e0981f316a6a02d0cf1e9
https://github.com/siemens/jailhouse/commit/8384f472bc9f509b2c0e0981f316a6a02d0cf1e9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M tools/Makefile
Log Message:
-----------
tools: Include EXTRA_CFLAGS into build
This allows to pass in additional flags or override existing ones, just
like it is already possible for the parts under Kbuild control.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: cf123b368412c9d7f1efcb5a7d3e6f4f5ba990a5
https://github.com/siemens/jailhouse/commit/cf123b368412c9d7f1efcb5a7d3e6f4f5ba990a5
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M Kbuild
M tools/Makefile
Log Message:
-----------
Enforce zero warnings
Break the build in case of warnings. Can still be temporarily
overwritten by appending EXTRA_CFLAGS=-Wno-error to a build.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d747205eec4bb66e95b1de426d618a8c6d34d61a
https://github.com/siemens/jailhouse/commit/d747205eec4bb66e95b1de426d618a8c6d34d61a
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M .gitignore
Log Message:
-----------
gitignore: Remove user-specific rules
A project's .gitignore should be about project-specific rules, shared by
everyone compiling it. So, instead of adding more and more rules for
user-specific editors or tools, remove them completely and no longer
accept new ones. Users can easily define local rules, see gitignore man
page.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: bf96fe4922710b75cc4c28022d3235fda83c1bf3
https://github.com/siemens/jailhouse/commit/bf96fe4922710b75cc4c28022d3235fda83c1bf3
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Fix byte-wise write access to GICD_ITARGETSRn
While expanding byte accesses to full words, we forgot to adjust the
address as well. This led to unaligned word accesses on writes, followed
by hypervisor aborts.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 7287a5a75cab2e0075c1d997b727ab740f81db5a
https://github.com/siemens/jailhouse/commit/7287a5a75cab2e0075c1d997b727ab740f81db5a
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M .travis.yml
Log Message:
-----------
ci: Update CA certificates to unbreak Coverity build
See https://github.com/travis-ci/docs-travis-ci-com/pull/617
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: eda93050c75d3f3ef4509d3faccc451b0946b607
https://github.com/siemens/jailhouse/commit/eda93050c75d3f3ef4509d3faccc451b0946b607
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M driver/main.c
M hypervisor/arch/arm/include/asm/jailhouse_hypercall.h
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M hypervisor/setup.c
Log Message:
-----------
driver: ioremap the hypervisor firmware to any kernel address
At the moment the Linux driver maps the Jailhouse binary to
JAILHOUSE_BASE. The underlying assumption is that Linux may map the
firmware (in the Linux kernel space), to the same virtual address it
has been built to run from.
This assumption is unworkable on ARMv8 processors running in AArch64
mode. Kernel memory is allocated in a high address region, that is
not addressable from EL2, where the hypervisor will run from.
This patch removes the assumption, by introducing the
JAILHOUSE_BORROW_ROOT_PT define, which signals the behavior of the
current architectures.
We also turn the entry point in the header, into an offset from the
Jailhouse load address, so we can enter the image regardless of
where it will be mapped.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 37f0f7e117964c0c24a67485d3e8ca4781fab734
https://github.com/siemens/jailhouse/commit/37f0f7e117964c0c24a67485d3e8ca4781fab734
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M driver/cell.c
M driver/main.c
Log Message:
-----------
driver: sync I-cache, D-cache and memory
Syncronize I-cache with D-cache after loading the hypervisor
image or a cell image. This must be done in arm64 according to
ARMv8 ARM spec. See page 1712, D3.4.6 "Non-cacheable accesses
and instruction caches".
This patch fixes coherency problems observed on real HW targets.
On x86 this operation is a NOP.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: edited comments]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 49a683f3a3823a445d88a2021dc69993d6edff8b
https://github.com/siemens/jailhouse/commit/49a683f3a3823a445d88a2021dc69993d6edff8b
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/arch/x86/apic.c
M hypervisor/arch/x86/control.c
M hypervisor/include/jailhouse/printk.h
M hypervisor/include/jailhouse/processor.h
M hypervisor/printk.c
Log Message:
-----------
core: make phys_processor_id() return unsigned long
32 bits ought not be enough for anybody.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 11cc0e0cf21d53544bfe19977af1520981769e34
https://github.com/siemens/jailhouse/commit/11cc0e0cf21d53544bfe19977af1520981769e34
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/control.c
Log Message:
-----------
core: panic_stop: print current cell only if it has been set
Currently during a panic, panic_stop will print the current cell
on the CPU where the panic occurred. However, if the hypervisor
panics sufficiently early during initialization, we may end up in
a situation where the root cell has not been initialized. This can
easily cause a trap loop, making the panic output less useful.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6b74f910dc248be969f16dc57e12412412f41b36
https://github.com/siemens/jailhouse/commit/6b74f910dc248be969f16dc57e12412412f41b36
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/x86/include/asm/paging.h
M hypervisor/include/jailhouse/paging.h
M hypervisor/paging.c
Log Message:
-----------
core: Add support for aligned page allocation
Refactor page_alloc to page_alloc_internal which accepts an additional
constraint for its allocation: align_mask. The allocated region will now
have its start page chosen so that page_number & align_mask is zero. If
no alignment is required, align_mask just needs to be set to 0. This is
what page_alloc exploits.
However, the new function page_alloc_aligned is introduces to return
page regions aligned according to their size (num pages will be aligned
by num * PAGE_SIZE). This implied that num needs to be a power of two.
This will be used on the AArch64 port of Jailhouse to support physical
address ranges from 40 to 44 bits: in these configurations, the initial
page table level may take up multiple consecutive pages.
Based on patch by Antonios Motakis.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: af24262ac5020eda9da14db3ab2e84f8297fd4a2
https://github.com/siemens/jailhouse/commit/af24262ac5020eda9da14db3ab2e84f8297fd4a2
Author: Claudio Fontana <claudio...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/lib.c
Log Message:
-----------
core: lib: replace ARM memcpy implementation with generic version
Remove the memcpy implementation from the ARM port, and add a
generic version to the core library for all architectures.
Signed-off-by: Claudio Fontana <claudio...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: removed all signs of weakness!]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6936d5c860976325b6cd4e2fb30f251db0f133fd
https://github.com/siemens/jailhouse/commit/6936d5c860976325b6cd4e2fb30f251db0f133fd
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/control.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/lib.c
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm/setup.c
Log Message:
-----------
arm: psci: support multiple affinity levels in MPIDR
PSCI actually takes CPU parameters by the MPIDR id, which may
differ from the logical id of the CPU. This patch is the first step
into properly handling the CPU affinity levels in the MPIDR.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[Jan: add missing processor.h include to setup.c]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f404b89d34d44bd23dba889d495564c1fbed992d
https://github.com/siemens/jailhouse/commit/f404b89d34d44bd23dba889d495564c1fbed992d
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
M hypervisor/arch/arm/traps.c
Log Message:
-----------
arm: replace IS_PSCI_FN macro with more explicit versions
The previous version of the macro allows for more false positives
than necessary.
Replace the macro with IS_PSCI_32 and IS_PSCI_UBOOT macros, that
explicitly check for the 32 bit PSCI IDs, and the PSCI 0.1 IDs
used by uboot. ARMv8 will need an additinal check for the IDs
of 64 bit PSCI functions.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d
https://github.com/siemens/jailhouse/commit/bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: move the handle_irq_route function to the GICv3 module
The handle_irq_route function is not needed with the GICv2.
On the ARMv8 port we will not assign a virt_id to each CPU,
opting to use the MPIDR as much as we can from the start.
GICv3 will need heavier refactoring for this purpose; by moving
this function we can reuse the GICv2 code on ARMv8.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[Jan: implement stub in v2 to reduce #ifdefs]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b2b588833a6e9ade955a723242072120de9f1354
https://github.com/siemens/jailhouse/commit/b2b588833a6e9ade955a723242072120de9f1354
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/include/asm/paging_modes.h
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/arm/paging.c
Log Message:
-----------
arm: prepare port for 48 bit PARange support
We currently support 3 levels of page tables for a 39 bits PA range
on ARM. This patch implements support for 4 level page tables,
and 3 level page tables with a concatenated level 1 root page
table.
On AArch32 we stick with the current restriction of building for
a 39 bit physical address space; however this change will allow
us to support a 40 to 48 bit PARange on AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 0c0a0086c1deabf39aad0d3f0320da2874603139
https://github.com/siemens/jailhouse/commit/0c0a0086c1deabf39aad0d3f0320da2874603139
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: put the value of VTCR for cells in a define
We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the
AArch64 port, save for the value we use for the VTCRL. AArch64 will
need in addition to the flags set by the AArch32 port, to set the
size of the address space.
We put this behind a define in asm/paging.h to allow this reuse.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6
https://github.com/siemens/jailhouse/commit/89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/processor.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: hide TLB flush behind a macro
Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: c75977ab419f15af28aa57a03dcc2dccdec62428
https://github.com/siemens/jailhouse/commit/c75977ab419f15af28aa57a03dcc2dccdec62428
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
arm: Remove unused struct pending_irq
Leftover of 8b121b498b.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d99b6e21844e3c99b7195346a08611b3cd46a057
https://github.com/siemens/jailhouse/commit/d99b6e21844e3c99b7195346a08611b3cd46a057
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M configs/bananapi.c
M configs/f2a88xm-hd3.c
M configs/h87i.c
M configs/imb-a180.c
M configs/ioapic-demo.c
M configs/jetson-tk1.c
M configs/qemu-vm.c
M configs/vexpress-linux-demo.c
M configs/vexpress.c
M hypervisor/arch/arm/irqchip.c
M hypervisor/arch/x86/ioapic.c
M hypervisor/include/jailhouse/cell-config.h
M tools/root-cell-config.c.tmpl
Log Message:
-----------
config, core: Improve irqchip configuration
This aims at supporting irqchips with more than 64 pins. The idea is to
use multiple entries in this case, each describing a distinct set of the
pins. Therefore, a pin_base field is introduced to jailhouse_irqchip.
Moreover, we expand the number of pins for each entry to 128.
We do not exploit the extended pin number on ARM yet, but stick with
64 pins for now. Succeeding change sets will tackle it.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f2931b157d70e7257da839588cb2a325dc2a0aa6
https://github.com/siemens/jailhouse/commit/f2931b157d70e7257da839588cb2a325dc2a0aa6
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/cell.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Use full bitmap to manage per-cell interrupt access
Commit: 85783c01aa07f911c6eab0f53536a82a7d207f2f
https://github.com/siemens/jailhouse/commit/85783c01aa07f911c6eab0f53536a82a7d207f2f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M configs/bananapi.c
M configs/vexpress-linux-demo.c
M configs/vexpress.c
Log Message:
-----------
config: Correct / comment GIC irqchip addresses
We will soon evaluate them, so their correct value starts to matter.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d14d1703a7f285a93fde6d3198ab639ec72bb0b8
https://github.com/siemens/jailhouse/commit/d14d1703a7f285a93fde6d3198ab639ec72bb0b8
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Rename reg parameter of handle_irq_target to irq
Reflects better what this is about.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b7857f0e03f4caea5b383a5722ce653bfd7e8ad5
https://github.com/siemens/jailhouse/commit/b7857f0e03f4caea5b383a5722ce653bfd7e8ad5
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Print IRQ number rather than SPI on handle_irq_target errors
Configuration and other reportings are based on absolute IDs as well.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 902ee9cfd32652f6926da709b259d46a68bdebf4
https://github.com/siemens/jailhouse/commit/902ee9cfd32652f6926da709b259d46a68bdebf4
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Rework spi_in_cell to irqchip_irq_in_cell
Make use of the the fully populated irq_bitmap and enhance spi_in_cell
to consider SGIs and PPIs as well. This allows to simplify
restrict_bitmask_access.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: ddc4a66cfa509b422a5c385783d2e863c7f875dd
https://github.com/siemens/jailhouse/commit/ddc4a66cfa509b422a5c385783d2e863c7f875dd
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/include/jailhouse/control.h
Log Message:
-----------
core: Introduce first_cpu
Extracted from patch of Antonios Motakis: Avoid the barely readable
"for_each_cpu(...) break;" pattern.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: da2bcc4252b488ad0740df9af6e2a5a90bc4f164
https://github.com/siemens/jailhouse/commit/da2bcc4252b488ad0740df9af6e2a5a90bc4f164
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove SPI target reset on cell destruction
There is no point in updating the SPI routing on cell destruction: all
CPUs the cell owned will be given back to the root cell. So any
previously written valid target configuration remain valid.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: a70819d9adfb29cd096c3ef2e8cafe83a8ff21e1
https://github.com/siemens/jailhouse/commit/a70819d9adfb29cd096c3ef2e8cafe83a8ff21e1
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Fold irqchip_root_cell_shrink into irqchip_cell_init
Simplifies the code.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 0456bcecbe7d4b1ca159f996a7706c3ec6e3391c
https://github.com/siemens/jailhouse/commit/0456bcecbe7d4b1ca159f996a7706c3ec6e3391c
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: Factor out gic_targets_in_cell
We will reuse it for affinity adjustments on cell creation.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 90e7060810f2adab5b7646150b9f465014855ed1
https://github.com/siemens/jailhouse/commit/90e7060810f2adab5b7646150b9f465014855ed1
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Validate ARE-NS being enabled with GICv3
Linux does enable Affinity Routing, but better check because the code
depends on this.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 011ab917a15057f52d36b1542bf3454abec55160
https://github.com/siemens/jailhouse/commit/011ab917a15057f52d36b1542bf3454abec55160
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Rework interrupt affinity management on cell creation
So far, we only ensured that the affinities of interrupts given to new
cells match with the corresponding CPU set. However, we also need to
check that Linux properly adjusted the affinity of all its remaining
interrupts properly.
This introduces a new irqchip callback adjust_irq_target which performs
the check and the potential adjustment to the first CPU of a cell on a
per-interrupt basis. A single loop in irqchip_cell_init triggers them.
gic_target_spis and gic_route_spis become obsolete.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 51f3bdab18fe814430b7d01886494f532d9f4566
https://github.com/siemens/jailhouse/commit/51f3bdab18fe814430b7d01886494f532d9f4566
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-28 (Tue, 28 Jun 2016)
Changed paths:
M tools/jailhouse-config-create
Log Message:
-----------
tools: config-create: Do not enter infinite over disabled PCI devices
If a PCI device is disabled, e.g. a secondary GPU, we may not see its
config space anymore while it is still listed. With config all 0xff, we
will then enter an infinite loop while trying to make sense of the
capability list. Prevent this, issuing a warning that we will skip this
device.
Reported-by: Thomas Pettinger <thomas.p...@tum.de>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/425f61a96683...51f3bdab18fe
Home: https://github.com/siemens/jailhouse
Commit: 314922e8bb720d917e44906600a29ef6185b74ac
https://github.com/siemens/jailhouse/commit/314922e8bb720d917e44906600a29ef6185b74ac
Author: Xuguo Wang <hudd...@gmail.com>
Date: 2016-05-31 (Tue, 31 May 2016)
Changed paths:
M inmates/lib/cmdline.c
Log Message:
-----------
inmates/lib: cmdline.c
There is no point in checking for *p == 0 in the while loop,
after over the blanks, then checking for the parameters, if
find, return true, otherwise continue check the parameters,
if to the end of the cmdline, return false.
Signed-off-by: Xuguo Wang <hudd...@gmail.com>
[Jan: also removed curly braces]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 3cfdd3aba4bb9a91bef54298522812ffcc22b3af
https://github.com/siemens/jailhouse/commit/3cfdd3aba4bb9a91bef54298522812ffcc22b3af
Author: Ralf Ramsauer <ra...@ramses-pyramidenbau.de>
Date: 2016-06-13 (Mon, 13 Jun 2016)
Changed paths:
M tools/jailhouse-config-create
Log Message:
-----------
tools: simplify python statement
Signed-off-by: Ralf Ramsauer <ra...@ramses-pyramidenbau.de>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: fe6decf9d3b9a4fd8412f2dbc0d939b965dcc073
https://github.com/siemens/jailhouse/commit/fe6decf9d3b9a4fd8412f2dbc0d939b965dcc073
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-13 (Mon, 13 Jun 2016)
Changed paths:
M hypervisor/arch/x86/amd_iommu.c
M hypervisor/arch/x86/include/asm/amd_iommu.h
Log Message:
-----------
x86: Add missing include to amd_iommu.h
Reported by header-check script: We need this in the header due to the
use of struct jailhouse_memory. Consequently, we can remove the include
from the corresponding amd_iommu.c.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6b7bef821e30d07f3a922c60ba34da623b2a0b31
https://github.com/siemens/jailhouse/commit/6b7bef821e30d07f3a922c60ba34da623b2a0b31
Author: cyng93 <cyn...@gmail.com>
Date: 2016-06-15 (Wed, 15 Jun 2016)
Changed paths:
A Documentation/setup-on-banana-pi-arm-board.md
M README.md
Log Message:
-----------
Documentation: Move BananaPi-related docs out
This patch move BananaPi-related documentation out from `README.md` to
`Documentation/setup-on-banana-pi-arm-board.md`
Signed-off-by: CHING-YI NG <cyn...@gmail.com>
[Jan: removed some blank lines from README.md]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 60121418e65109e6280d6aa591d6558b66dab70b
https://github.com/siemens/jailhouse/commit/60121418e65109e6280d6aa591d6558b66dab70b
Author: cyng93 <cyn...@gmail.com>
Date: 2016-06-15 (Wed, 15 Jun 2016)
Changed paths:
M Documentation/setup-on-banana-pi-arm-board.md
Log Message:
-----------
Documentation: More BananaPi documentation
This patch include more details about how to setup Jailhouse on a BananaPi-M1 board.
Basically this documentation covered:
1. Installation of Bananian(BananaPi offical OS) on BananaPi
2. Modifying U-boot configuration on BananaPi to run Jailhouse.
3. Update Bananian to newer kernel so Jailhouse could works.
- Compiling Kernel.
- Installing Kernel.
4. Installing Jailhouse on BananaPi.
5. Simple demo/test: Running Jailhouse with Freertos-cell on BananaPi.
Signed-off-by: CHING-YI NG <cyn...@gmail.com>
[Jan: removed external media link showing FUSE selection - not needed]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: a9f949b08350538dd52d28c4477f4fcb902b3848
https://github.com/siemens/jailhouse/commit/a9f949b08350538dd52d28c4477f4fcb902b3848
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-15 (Wed, 15 Jun 2016)
Changed paths:
M Documentation/setup-on-banana-pi-arm-board.md
Log Message:
-----------
Documentation: Rewrap Banana Pi README to 80 chars
For better readability in the absence of a markdown viewer.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: da353b5769a2a2266f206c1d0e53402e4b99386c
https://github.com/siemens/jailhouse/commit/da353b5769a2a2266f206c1d0e53402e4b99386c
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/asm-defines.c
M hypervisor/arch/arm/entry.S
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/setup.c
Log Message:
-----------
arm: Use asm-defines.h for struct per_cpu members
Port the logic over from x86 and also drop CHECK_ASSUMPTION here.
The only slightly ugly detail: the PERCPU_SIZE_SHIFT define is now
duplicated in both asm/percpu.h instances because there is no good
generic header yet to hold it. Can be cleaned up later on.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: fd447ceecb0e2555d017c3b73c9bd5d9b62f1436
https://github.com/siemens/jailhouse/commit/fd447ceecb0e2555d017c3b73c9bd5d9b62f1436
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/smp-vexpress.c
Log Message:
-----------
arm: Add missing printk.h include
Some implicit inclusion disappeared.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 7c2644bf2bd841b5d97a8f94856eb57b753a2ef9
https://github.com/siemens/jailhouse/commit/7c2644bf2bd841b5d97a8f94856eb57b753a2ef9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Fix build warning in gic-v3
Leftover from the mmio_perform_access refactoring.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 315273ebcf6d3cc2c28bc3744118fb2f66a72a54
https://github.com/siemens/jailhouse/commit/315273ebcf6d3cc2c28bc3744118fb2f66a72a54
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
arm: Remove unneeded include from irqchip.h
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 0e82670826fd2283d7eb032a3eb11ccf8013c815
https://github.com/siemens/jailhouse/commit/0e82670826fd2283d7eb032a3eb11ccf8013c815
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Un-inline spi_in_cell
To big to be inlined, and we also want to avoid dereferencing struct
cell in the header due to upcoming include reordering.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 03475882880dc5ae49d0852c628a8b8958be80ac
https://github.com/siemens/jailhouse/commit/03475882880dc5ae49d0852c628a8b8958be80ac
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove write-only priority field from pending_irq
We do not support interrupt priorities so far, and we may have to model
them differently into queues once we do. Remove the de facto unused
field.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 3b6a758cb690553583fab3156bce14114775e726
https://github.com/siemens/jailhouse/commit/3b6a758cb690553583fab3156bce14114775e726
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove maintenance flag from pending_irq.type.sgi
It was always cleared.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d62540a7a2a5a6c769550bd250c359bea3910795
https://github.com/siemens/jailhouse/commit/d62540a7a2a5a6c769550bd250c359bea3910795
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove hw flag from pending_irq
Can be derived from virt_id.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 05c1d67e0a7913f967a49a76de8cf93dafba1489
https://github.com/siemens/jailhouse/commit/05c1d67e0a7913f967a49a76de8cf93dafba1489
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove cpuid from pending_irq
Was always set to 0.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 35a46c75c5eb577c9c780340cdbc92d844d1eaca
https://github.com/siemens/jailhouse/commit/35a46c75c5eb577c9c780340cdbc92d844d1eaca
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove irq field from pending_irq
Always identical to virt_id.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b77b9793126fd278ec3839cbead5bf21a389bdd0
https://github.com/siemens/jailhouse/commit/b77b9793126fd278ec3839cbead5bf21a389bdd0
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove return code from irqchip_inject_pending
It's always 0.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f5dcc13bcf89d190d35b99cf79a8586ea7c1a93d
https://github.com/siemens/jailhouse/commit/f5dcc13bcf89d190d35b99cf79a8586ea7c1a93d
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove unused return code of irqchip_set_pending
No caller evaluated it so far, and none of them has a use case for it.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 35b1928d4977040a4a9f4fc1f2a093882182a953
https://github.com/siemens/jailhouse/commit/35b1928d4977040a4a9f4fc1f2a093882182a953
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Disable maintenance interrupt on successful injection
We enable the maintenance interrupt when all list registers are in use.
However, there was no disabling of it again. Apparently, it rarely
triggered in the field, otherwise we would have seen a lot of
maintenance interrupt storms, thus locked-up systems.
This introduces another callback to enable or disable the maintenance
interrupt. It is now controlled by irqchip_inject_pending, the function
that is also called when handling a maintenance interrupt.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 9fc9f67f05c9fbe872f647a0d47f54e7dbb9b90f
https://github.com/siemens/jailhouse/commit/9fc9f67f05c9fbe872f647a0d47f54e7dbb9b90f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Make sure to not queue interrupt that were rejected as duplicates
If the inject_irq callback detect that an interrupt is already queued
in some list register, do not insert it into the software queue, thus
coalesce the event like real hardware does.
The change in the return code of inject_irq is more cosmetic, to reflect
the meaning better.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8b121b498b6e2f204c9b128b42e5423118be220b
https://github.com/siemens/jailhouse/commit/8b121b498b6e2f204c9b128b42e5423118be220b
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Convert software queue of pending interrupts into a ring
This massively simplifies the code and reduces the memory usage in
struct per_cpu. However, adding interrupt priorities later on may
require another rework.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: c8a9a6f84885c366160a394aaaf08715e426eaf4
https://github.com/siemens/jailhouse/commit/c8a9a6f84885c366160a394aaaf08715e426eaf4
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove try_inject parameter from irqchip_set_pending
We can only perform injection (and we also always want to) if target
CPU equals caller CPU, and this is better checked inside the function.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: e24bab3f5e70d877d470659569f22e2838813d0f
https://github.com/siemens/jailhouse/commit/e24bab3f5e70d877d470659569f22e2838813d0f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Enable maintenance interrupt also from irqchip_set_pending
In case we set an interrupt pending for the local CPU and cannot queue
it with the hardware, make sure the maintenance interrupt is on.
Otherwise, we risk to delay guest interrupts or cause the guest to get
stuck.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6f28047e0f4d78af4a712e6f1f2824e9a030a888
https://github.com/siemens/jailhouse/commit/6f28047e0f4d78af4a712e6f1f2824e9a030a888
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-16 (Thu, 16 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Enable / disable maintenance interrupt in distributor
We did not get any maintenance interrupts so far because we didn't
enable the source in the distributor so far. Fix this, but also disable
it again when shutting down.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8bf054eec255f83dcb98960f8de2508ff4a1d92d
https://github.com/siemens/jailhouse/commit/8bf054eec255f83dcb98960f8de2508ff4a1d92d
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Protect hypervisor used SGIs and PPIs from cell changes
We must not allow the cells to manipulate distributor registers or
register bits related to the hypervisor SGIs or the maintenance
interrupt.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 313bfa1a1f9b126dcbbe467ac60f1f35c6a82c61
https://github.com/siemens/jailhouse/commit/313bfa1a1f9b126dcbbe467ac60f1f35c6a82c61
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Make cpu_init and cpu_reset callbacks mandatory
No need for checking them to be NULL, we need them in both
implementations.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f4aa33bef18a6a17069f46915b92ea935e78b107
https://github.com/siemens/jailhouse/commit/f4aa33bef18a6a17069f46915b92ea935e78b107
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Reject unknown GIC versions
We would likely crash anyway due to irqchip containing only NULL
pointers.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6e68f512b1cb75c3b07feb898eea17f032ec1378
https://github.com/siemens/jailhouse/commit/6e68f512b1cb75c3b07feb898eea17f032ec1378
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Consolidate gic_irqchip to irqchip
Likely, we will never support alternative irqchips to the GIC (only
cascaded ones). So this copying-over is not required.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 8384f472bc9f509b2c0e0981f316a6a02d0cf1e9
https://github.com/siemens/jailhouse/commit/8384f472bc9f509b2c0e0981f316a6a02d0cf1e9
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M tools/Makefile
Log Message:
-----------
tools: Include EXTRA_CFLAGS into build
This allows to pass in additional flags or override existing ones, just
like it is already possible for the parts under Kbuild control.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: cf123b368412c9d7f1efcb5a7d3e6f4f5ba990a5
https://github.com/siemens/jailhouse/commit/cf123b368412c9d7f1efcb5a7d3e6f4f5ba990a5
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M Kbuild
M tools/Makefile
Log Message:
-----------
Enforce zero warnings
Break the build in case of warnings. Can still be temporarily
overwritten by appending EXTRA_CFLAGS=-Wno-error to a build.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d747205eec4bb66e95b1de426d618a8c6d34d61a
https://github.com/siemens/jailhouse/commit/d747205eec4bb66e95b1de426d618a8c6d34d61a
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M .gitignore
Log Message:
-----------
gitignore: Remove user-specific rules
A project's .gitignore should be about project-specific rules, shared by
everyone compiling it. So, instead of adding more and more rules for
user-specific editors or tools, remove them completely and no longer
accept new ones. Users can easily define local rules, see gitignore man
page.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: bf96fe4922710b75cc4c28022d3235fda83c1bf3
https://github.com/siemens/jailhouse/commit/bf96fe4922710b75cc4c28022d3235fda83c1bf3
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Fix byte-wise write access to GICD_ITARGETSRn
While expanding byte accesses to full words, we forgot to adjust the
address as well. This led to unaligned word accesses on writes, followed
by hypervisor aborts.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 7287a5a75cab2e0075c1d997b727ab740f81db5a
https://github.com/siemens/jailhouse/commit/7287a5a75cab2e0075c1d997b727ab740f81db5a
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M .travis.yml
Log Message:
-----------
ci: Update CA certificates to unbreak Coverity build
See https://github.com/travis-ci/docs-travis-ci-com/pull/617
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: eda93050c75d3f3ef4509d3faccc451b0946b607
https://github.com/siemens/jailhouse/commit/eda93050c75d3f3ef4509d3faccc451b0946b607
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M driver/main.c
M hypervisor/arch/arm/include/asm/jailhouse_hypercall.h
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M hypervisor/setup.c
Log Message:
-----------
driver: ioremap the hypervisor firmware to any kernel address
At the moment the Linux driver maps the Jailhouse binary to
JAILHOUSE_BASE. The underlying assumption is that Linux may map the
firmware (in the Linux kernel space), to the same virtual address it
has been built to run from.
This assumption is unworkable on ARMv8 processors running in AArch64
mode. Kernel memory is allocated in a high address region, that is
not addressable from EL2, where the hypervisor will run from.
This patch removes the assumption, by introducing the
JAILHOUSE_BORROW_ROOT_PT define, which signals the behavior of the
current architectures.
We also turn the entry point in the header, into an offset from the
Jailhouse load address, so we can enter the image regardless of
where it will be mapped.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 37f0f7e117964c0c24a67485d3e8ca4781fab734
https://github.com/siemens/jailhouse/commit/37f0f7e117964c0c24a67485d3e8ca4781fab734
Author: Dmitry Voytik <dmitry...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M driver/cell.c
M driver/main.c
Log Message:
-----------
driver: sync I-cache, D-cache and memory
Syncronize I-cache with D-cache after loading the hypervisor
image or a cell image. This must be done in arm64 according to
ARMv8 ARM spec. See page 1712, D3.4.6 "Non-cacheable accesses
and instruction caches".
This patch fixes coherency problems observed on real HW targets.
On x86 this operation is a NOP.
Signed-off-by: Dmitry Voytik <dmitry...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: edited comments]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 49a683f3a3823a445d88a2021dc69993d6edff8b
https://github.com/siemens/jailhouse/commit/49a683f3a3823a445d88a2021dc69993d6edff8b
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/arch/x86/apic.c
M hypervisor/arch/x86/control.c
M hypervisor/include/jailhouse/printk.h
M hypervisor/include/jailhouse/processor.h
M hypervisor/printk.c
Log Message:
-----------
core: make phys_processor_id() return unsigned long
32 bits ought not be enough for anybody.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 11cc0e0cf21d53544bfe19977af1520981769e34
https://github.com/siemens/jailhouse/commit/11cc0e0cf21d53544bfe19977af1520981769e34
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/control.c
Log Message:
-----------
core: panic_stop: print current cell only if it has been set
Currently during a panic, panic_stop will print the current cell
on the CPU where the panic occurred. However, if the hypervisor
panics sufficiently early during initialization, we may end up in
a situation where the root cell has not been initialized. This can
easily cause a trap loop, making the panic output less useful.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6b74f910dc248be969f16dc57e12412412f41b36
https://github.com/siemens/jailhouse/commit/6b74f910dc248be969f16dc57e12412412f41b36
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/x86/include/asm/paging.h
M hypervisor/include/jailhouse/paging.h
M hypervisor/paging.c
Log Message:
-----------
core: Add support for aligned page allocation
Refactor page_alloc to page_alloc_internal which accepts an additional
constraint for its allocation: align_mask. The allocated region will now
have its start page chosen so that page_number & align_mask is zero. If
no alignment is required, align_mask just needs to be set to 0. This is
what page_alloc exploits.
However, the new function page_alloc_aligned is introduces to return
page regions aligned according to their size (num pages will be aligned
by num * PAGE_SIZE). This implied that num needs to be a power of two.
This will be used on the AArch64 port of Jailhouse to support physical
address ranges from 40 to 44 bits: in these configurations, the initial
page table level may take up multiple consecutive pages.
Based on patch by Antonios Motakis.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: af24262ac5020eda9da14db3ab2e84f8297fd4a2
https://github.com/siemens/jailhouse/commit/af24262ac5020eda9da14db3ab2e84f8297fd4a2
Author: Claudio Fontana <claudio...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/lib.c
Log Message:
-----------
core: lib: replace ARM memcpy implementation with generic version
Remove the memcpy implementation from the ARM port, and add a
generic version to the core library for all architectures.
Signed-off-by: Claudio Fontana <claudio...@huawei.com>
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[antonios...@huawei.com: removed all signs of weakness!]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 6936d5c860976325b6cd4e2fb30f251db0f133fd
https://github.com/siemens/jailhouse/commit/6936d5c860976325b6cd4e2fb30f251db0f133fd
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/control.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/lib.c
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm/setup.c
Log Message:
-----------
arm: psci: support multiple affinity levels in MPIDR
PSCI actually takes CPU parameters by the MPIDR id, which may
differ from the logical id of the CPU. This patch is the first step
into properly handling the CPU affinity levels in the MPIDR.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[Jan: add missing processor.h include to setup.c]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f404b89d34d44bd23dba889d495564c1fbed992d
https://github.com/siemens/jailhouse/commit/f404b89d34d44bd23dba889d495564c1fbed992d
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
M hypervisor/arch/arm/traps.c
Log Message:
-----------
arm: replace IS_PSCI_FN macro with more explicit versions
The previous version of the macro allows for more false positives
than necessary.
Replace the macro with IS_PSCI_32 and IS_PSCI_UBOOT macros, that
explicitly check for the 32 bit PSCI IDs, and the PSCI 0.1 IDs
used by uboot. ARMv8 will need an additinal check for the IDs
of 64 bit PSCI functions.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d
https://github.com/siemens/jailhouse/commit/bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: move the handle_irq_route function to the GICv3 module
The handle_irq_route function is not needed with the GICv2.
On the ARMv8 port we will not assign a virt_id to each CPU,
opting to use the MPIDR as much as we can from the start.
GICv3 will need heavier refactoring for this purpose; by moving
this function we can reuse the GICv2 code on ARMv8.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
[Jan: implement stub in v2 to reduce #ifdefs]
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b2b588833a6e9ade955a723242072120de9f1354
https://github.com/siemens/jailhouse/commit/b2b588833a6e9ade955a723242072120de9f1354
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/include/asm/paging_modes.h
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/arm/paging.c
Log Message:
-----------
arm: prepare port for 48 bit PARange support
We currently support 3 levels of page tables for a 39 bits PA range
on ARM. This patch implements support for 4 level page tables,
and 3 level page tables with a concatenated level 1 root page
table.
On AArch32 we stick with the current restriction of building for
a 39 bit physical address space; however this change will allow
us to support a 40 to 48 bit PARange on AArch64.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 0c0a0086c1deabf39aad0d3f0320da2874603139
https://github.com/siemens/jailhouse/commit/0c0a0086c1deabf39aad0d3f0320da2874603139
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: put the value of VTCR for cells in a define
We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the
AArch64 port, save for the value we use for the VTCRL. AArch64 will
need in addition to the flags set by the AArch32 port, to set the
size of the address space.
We put this behind a define in asm/paging.h to allow this reuse.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6
https://github.com/siemens/jailhouse/commit/89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6
Author: Antonios Motakis <antonios...@huawei.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/processor.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: hide TLB flush behind a macro
Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <antonios...@huawei.com>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: c75977ab419f15af28aa57a03dcc2dccdec62428
https://github.com/siemens/jailhouse/commit/c75977ab419f15af28aa57a03dcc2dccdec62428
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
arm: Remove unused struct pending_irq
Leftover of 8b121b498b.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d99b6e21844e3c99b7195346a08611b3cd46a057
https://github.com/siemens/jailhouse/commit/d99b6e21844e3c99b7195346a08611b3cd46a057
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M configs/bananapi.c
M configs/f2a88xm-hd3.c
M configs/h87i.c
M configs/imb-a180.c
M configs/ioapic-demo.c
M configs/jetson-tk1.c
M configs/qemu-vm.c
M configs/vexpress-linux-demo.c
M configs/vexpress.c
M hypervisor/arch/arm/irqchip.c
M hypervisor/arch/x86/ioapic.c
M hypervisor/include/jailhouse/cell-config.h
M tools/root-cell-config.c.tmpl
Log Message:
-----------
config, core: Improve irqchip configuration
This aims at supporting irqchips with more than 64 pins. The idea is to
use multiple entries in this case, each describing a distinct set of the
pins. Therefore, a pin_base field is introduced to jailhouse_irqchip.
Moreover, we expand the number of pins for each entry to 128.
We do not exploit the extended pin number on ARM yet, but stick with
64 pins for now. Succeeding change sets will tackle it.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: f2931b157d70e7257da839588cb2a325dc2a0aa6
https://github.com/siemens/jailhouse/commit/f2931b157d70e7257da839588cb2a325dc2a0aa6
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/cell.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Use full bitmap to manage per-cell interrupt access
Commit: 85783c01aa07f911c6eab0f53536a82a7d207f2f
https://github.com/siemens/jailhouse/commit/85783c01aa07f911c6eab0f53536a82a7d207f2f
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M configs/bananapi.c
M configs/vexpress-linux-demo.c
M configs/vexpress.c
Log Message:
-----------
config: Correct / comment GIC irqchip addresses
We will soon evaluate them, so their correct value starts to matter.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: d14d1703a7f285a93fde6d3198ab639ec72bb0b8
https://github.com/siemens/jailhouse/commit/d14d1703a7f285a93fde6d3198ab639ec72bb0b8
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Rename reg parameter of handle_irq_target to irq
Reflects better what this is about.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: b7857f0e03f4caea5b383a5722ce653bfd7e8ad5
https://github.com/siemens/jailhouse/commit/b7857f0e03f4caea5b383a5722ce653bfd7e8ad5
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Print IRQ number rather than SPI on handle_irq_target errors
Configuration and other reportings are based on absolute IDs as well.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 902ee9cfd32652f6926da709b259d46a68bdebf4
https://github.com/siemens/jailhouse/commit/902ee9cfd32652f6926da709b259d46a68bdebf4
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Rework spi_in_cell to irqchip_irq_in_cell
Make use of the the fully populated irq_bitmap and enhance spi_in_cell
to consider SGIs and PPIs as well. This allows to simplify
restrict_bitmask_access.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: ddc4a66cfa509b422a5c385783d2e863c7f875dd
https://github.com/siemens/jailhouse/commit/ddc4a66cfa509b422a5c385783d2e863c7f875dd
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/include/jailhouse/control.h
Log Message:
-----------
core: Introduce first_cpu
Extracted from patch of Antonios Motakis: Avoid the barely readable
"for_each_cpu(...) break;" pattern.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: da2bcc4252b488ad0740df9af6e2a5a90bc4f164
https://github.com/siemens/jailhouse/commit/da2bcc4252b488ad0740df9af6e2a5a90bc4f164
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove SPI target reset on cell destruction
There is no point in updating the SPI routing on cell destruction: all
CPUs the cell owned will be given back to the root cell. So any
previously written valid target configuration remain valid.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: a70819d9adfb29cd096c3ef2e8cafe83a8ff21e1
https://github.com/siemens/jailhouse/commit/a70819d9adfb29cd096c3ef2e8cafe83a8ff21e1
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Fold irqchip_root_cell_shrink into irqchip_cell_init
Simplifies the code.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 0456bcecbe7d4b1ca159f996a7706c3ec6e3391c
https://github.com/siemens/jailhouse/commit/0456bcecbe7d4b1ca159f996a7706c3ec6e3391c
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: Factor out gic_targets_in_cell
We will reuse it for affinity adjustments on cell creation.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 90e7060810f2adab5b7646150b9f465014855ed1
https://github.com/siemens/jailhouse/commit/90e7060810f2adab5b7646150b9f465014855ed1
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Validate ARE-NS being enabled with GICv3
Linux does enable Affinity Routing, but better check because the code
depends on this.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 011ab917a15057f52d36b1542bf3454abec55160
https://github.com/siemens/jailhouse/commit/011ab917a15057f52d36b1542bf3454abec55160
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Rework interrupt affinity management on cell creation
So far, we only ensured that the affinities of interrupts given to new
cells match with the corresponding CPU set. However, we also need to
check that Linux properly adjusted the affinity of all its remaining
interrupts properly.
This introduces a new irqchip callback adjust_irq_target which performs
the check and the potential adjustment to the first CPU of a cell on a
per-interrupt basis. A single loop in irqchip_cell_init triggers them.
gic_target_spis and gic_route_spis become obsolete.
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Commit: 51f3bdab18fe814430b7d01886494f532d9f4566
https://github.com/siemens/jailhouse/commit/51f3bdab18fe814430b7d01886494f532d9f4566
Author: Jan Kiszka <jan.k...@siemens.com>
Date: 2016-06-28 (Tue, 28 Jun 2016)
Changed paths:
M tools/jailhouse-config-create
Log Message:
-----------
tools: config-create: Do not enter infinite over disabled PCI devices
If a PCI device is disabled, e.g. a secondary GPU, we may not see its
config space anymore while it is still listed. With config all 0xff, we
will then enter an infinite loop while trying to make sense of the
capability list. Prevent this, issuing a warning that we will skip this
device.
Reported-by: Thomas Pettinger <thomas.p...@tum.de>
Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Compare: https://github.com/siemens/jailhouse/compare/425f61a96683...51f3bdab18fe
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