[PATCH 5/6] x86: Expand x86_msi_vector to carry 64-bit address unconditionally

[Jan Kiszka]

This will allow to match on the whole address to check if we are
actually targeting the MSI address space.

Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
---
hypervisor/arch/x86/include/asm/apic.h | 7 +++----
hypervisor/arch/x86/pci.c | 8 ++++----
2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/hypervisor/arch/x86/include/asm/apic.h b/hypervisor/arch/x86/include/asm/apic.h
index cfff890..d2cd632 100644
--- a/hypervisor/arch/x86/include/asm/apic.h
+++ b/hypervisor/arch/x86/include/asm/apic.h
@@ -1,7 +1,7 @@
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
- * Copyright (c) Siemens AG, 2013
+ * Copyright (c) Siemens AG, 2013-2017
*
* Authors:
* Jan Kiszka <jan.k...@siemens.com>
@@ -103,13 +103,12 @@

union x86_msi_vector {
struct {
- u32 unused:2,
+ u64 unused:2,
dest_logical:1,
redir_hint:1,
reserved1:8,
destination:8,
- address:12;
- u32 reserved2;
+ address:44;
u32 vector:8,
delivery_mode:3,
reserved:21;
diff --git a/hypervisor/arch/x86/pci.c b/hypervisor/arch/x86/pci.c
index cd22742..19d0ea9 100644
--- a/hypervisor/arch/x86/pci.c
+++ b/hypervisor/arch/x86/pci.c
@@ -1,7 +1,7 @@
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
- * Copyright (c) Siemens AG, 2014
+ * Copyright (c) Siemens AG, 2014-2017
*
* Authors:
* Ivan Kolchin <ivan.k...@siemens.com>
@@ -310,7 +310,7 @@ void arch_pci_suppress_msi(struct pci_device *device,
}
}

-static u32 pci_get_x86_msi_remap_address(unsigned int index)
+static u64 pci_get_x86_msi_remap_address(unsigned int index)
{
union x86_msi_vector msi = {
.remap.int_index15 = index >> 15,
@@ -320,7 +320,7 @@ static u32 pci_get_x86_msi_remap_address(unsigned int index)
.remap.address = MSI_ADDRESS_VALUE,
};

- return (u32)msi.raw.address;
+ return msi.raw.address;
}

int arch_pci_update_msi(struct pci_device *device,
@@ -358,7 +358,7 @@ int arch_pci_update_msi(struct pci_device *device,
if (info->msi_64bits)
pci_write_config(bdf, cap->start + 8, 0, 4);
pci_write_config(bdf, cap->start + 4,
- pci_get_x86_msi_remap_address(result), 4);
+ (u32)pci_get_x86_msi_remap_address(result), 4);

return 0;
}
--
2.1.4

[Jan Kiszka]

This ensures that no vector is left over from the previous usage that
could trigger unexpected or even invalid interrupts when the new user
starts configuring the device.

Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
---

hypervisor/pci.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/hypervisor/pci.c b/hypervisor/pci.c
index 913fde5..2f95dd7 100644
--- a/hypervisor/pci.c
+++ b/hypervisor/pci.c
@@ -577,10 +577,16 @@ void pci_reset_device(struct pci_device *device)
pci_write_config(device->info->bdf, PCI_CFG_COMMAND,
PCI_CMD_INTX_OFF, 2);

- for_each_pci_cap(cap, device, n)
+ for_each_pci_cap(cap, device, n) {
if (cap->id == PCI_CAP_MSI || cap->id == PCI_CAP_MSIX)
/* Disable MSI/MSI-X by clearing the control word. */
pci_write_config(device->info->bdf, cap->start+2, 0, 2);
+ if (cap->id == PCI_CAP_MSIX)
+ /* Mask each MSI-X vector also physically. */
+ for (n = 0; n < device->info->num_msix_vectors; n++)
+ mmio_write32(&device->msix_table[n].raw[3],
+ device->msix_vectors[n].raw[3]);
+ }
}

static int pci_add_physical_device(struct cell *cell, struct pci_device *device)
--
2.1.4

[Jan Kiszka]

A tiny low-cost board, based on the Allwinner H2+ with 4 Cortex-A7
cores. Configs are designed for the 256M variant. Make sure to reserve
the top 128M before running the non-root Linux inmate.

Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
---

configs/dts/inmate-orangepi0.dts | 108 ++++++++++++++++++++++++++++
configs/orangepi0-gic-demo.c | 63 +++++++++++++++++
configs/orangepi0-linux-demo.c | 100 ++++++++++++++++++++++++++
configs/orangepi0.c | 148 +++++++++++++++++++++++++++++++++++++++
inmates/lib/arm/include/mach.h | 9 +++
5 files changed, 428 insertions(+)
create mode 100644 configs/dts/inmate-orangepi0.dts
create mode 100644 configs/orangepi0-gic-demo.c
create mode 100644 configs/orangepi0-linux-demo.c
create mode 100644 configs/orangepi0.c

diff --git a/configs/dts/inmate-orangepi0.dts b/configs/dts/inmate-orangepi0.dts
new file mode 100644
index 0000000..effbabe
--- /dev/null
+++ b/configs/dts/inmate-orangepi0.dts
@@ -0,0 +1,108 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Device tree for Linux inmate test on Orange Pi Zero board,
+ * corresponds to configs/orangepi0-linux-demo.c
+ *
+ * Copyright (c) Siemens AG, 2016-2017
+ *
+ * Authors:
+ * Jan Kiszka <jan.k...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ model = "Jailhouse cell on Orange Pi Zero";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: clk24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ uart: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ };
+
+ vpci@2000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 123 0>,
+ <0 0 0 2 &gic GIC_SPI 124 0>,
+ <0 0 0 3 &gic GIC_SPI 125 0>,
+ <0 0 0 4 &gic GIC_SPI 126 0>;
+ reg = <0x2000000 0x100000>;
+ ranges =
+ <0x02000000 0x00 0x10000000 0x10000000 0x00 0x10000>;
+ };
+};
diff --git a/configs/orangepi0-gic-demo.c b/configs/orangepi0-gic-demo.c
new file mode 100644
index 0000000..3a1ab7b
--- /dev/null
+++ b/configs/orangepi0-gic-demo.c
@@ -0,0 +1,63 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for gic-demo inmate on Orange Pi Zero:
+ * 1 CPU, 64K RAM, serial ports 0-3, GPIO PA
+ *
+ * Copyright (c) Siemens AG, 2014-2016
+ *
+ * Authors:
+ * Jan Kiszka <jan.k...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[3];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "orangepi0-gic-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* GPIO: port A */ {
+ .phys_start = 0x01c20800,
+ .virt_start = 0x01c20800,
+ .size = 0x24,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* UART 0-3 */ {
+ .phys_start = 0x01c28000,
+ .virt_start = 0x01c28000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0x4f6f0000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ },
+};
diff --git a/configs/orangepi0-linux-demo.c b/configs/orangepi0-linux-demo.c
new file mode 100644
index 0000000..18d9f21
--- /dev/null
+++ b/configs/orangepi0-linux-demo.c
@@ -0,0 +1,100 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for linux-demo inmate on Orange Pi Zero:
+ * 1 CPU, 64M RAM, serial port 0
+ *

+ * Copyright (c) Siemens AG, 2014-2017

+ *
+ * Authors:
+ * Jan Kiszka <jan.k...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[4];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "orangepi0-linux-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG|JAILHOUSE_CELL_DEBUG_CONSOLE,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 123,
+ },
+
+ .cpus = {
+ 0xc,
+ },
+
+ .mem_regions = {
+ /* UART 0-3 */ {
+ .phys_start = 0x01c28000,
+ .virt_start = 0x01c28000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0x4f6f0000,
+ .virt_start = 0,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM */ {
+ .phys_start = 0x48000000,
+ .virt_start = 0x48000000,
+ .size = 0x76f0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* IVSHMEM shared memory region */ {
+ .phys_start = 0x4f700000,
+ .virt_start = 0x4f700000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x01c81000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (32-32), 0, 0, 1 << (155-128),
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 0x00,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .shmem_region = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
diff --git a/configs/orangepi0.c b/configs/orangepi0.c
new file mode 100644
index 0000000..a37e5d4
--- /dev/null
+++ b/configs/orangepi0.c
@@ -0,0 +1,148 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Test configuration for Orange Pi Zero (H2+ quad-core Cortex-A7, 256MB RAM)
+ *
+ * Copyright (c) Siemens AG, 2014-2016
+ *
+ * Authors:
+ * Jan Kiszka <jan.k...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[8];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .hypervisor_memory = {
+ .phys_start = 0x4f800000,
+ .size = 0x800000,
+ },
+ .debug_console = {
+ .address = 0x01c28000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_CON_TYPE_8250 |
+ JAILHOUSE_CON_FLAG_MMIO,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x2000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .arm = {
+ .gicd_base = 0x01c81000,
+ .gicc_base = 0x01c82000,
+ .gich_base = 0x01c84000,
+ .gicv_base = 0x01c86000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "Orange-Pi0",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 108,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* MMIO 1 (permissive) */ {
+ .phys_start = 0x01c00000,
+ .virt_start = 0x01c00000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pinctrl PA */ {
+ .phys_start = 0x01c20800,
+ .virt_start = 0x01c20800,
+ .size = 0x24,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* pinctrl rest */ {
+ .phys_start = 0x01c20824,
+ .virt_start = 0x01c20824,
+ .size = 0x3dc,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* watchdog */ {
+ .phys_start = 0x01c20ca0,
+ .virt_start = 0x01c20ca0,
+ .size = 0x20,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* MMIO 2 (permissive) */ {
+ .phys_start = 0x01c28000,
+ .virt_start = 0x01c28000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* MMIO 3 (permissive) */ {
+ .phys_start = 0x01f01000,
+ .virt_start = 0x01f01000,
+ .size = 0x3000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0xf700000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* IVSHMEM shared memory region */ {
+ .phys_start = 0x4f700000,
+ .virt_start = 0x4f700000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x01c81000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ },
+
+ .pci_devices = {
+ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 0x00,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .shmem_region = 7,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
diff --git a/inmates/lib/arm/include/mach.h b/inmates/lib/arm/include/mach.h
index 1d2cf51..a255947 100644
--- a/inmates/lib/arm/include/mach.h
+++ b/inmates/lib/arm/include/mach.h
@@ -39,6 +39,15 @@

#define TIMER_IRQ 27

+#elif defined(CONFIG_MACH_ORANGEPI0)
+#define CON_TYPE "8250"
+#define CON_BASE 0x01c28000
+
+#define GICD_V2_BASE ((void *)0x01c81000)
+#define GICC_V2_BASE ((void *)0x01c82000)
+
+#define TIMER_IRQ 27
+
#elif defined(CONFIG_MACH_VEXPRESS)
#define CON_TYPE "PL011"
#define CON_BASE 0x1c090000
--
2.1.4

[Jan Kiszka]

Linux seems to write zeros to MSI registers when unregistering an MSI
interrupt:

[...]
pci_bus_write_config_dword+0x14/0x20
__pci_write_msi_msg+0xcc/0x130
pci_msi_domain_write_msg+0x1d/0x20
msi_domain_deactivate+0x28/0x30 <-- this writes zeros
irq_domain_deactivate_irq+0x28/0x40
irq_shutdown+0x39/0x70
__free_irq+0x1ee/0x290
free_irq+0x34/0x80
tg3_test_interrupt+0x3f/0x230
tg3_start+0xfa3/0x1130
[...]
(taken with 4.9-rt)

Let's check if the target address actually matches the MSI address space
and, if not, simply declare the vector invalid. That will block it from
being used, raising an IOMMU runtime error at most when the device
should fire nevertheless. But we no longer panic the writer.

Signed-off-by: Jan Kiszka <jan.k...@siemens.com>
Tested-by: Rajiv Vaidyanath <Rajiv.Va...@ccur.com>
---
hypervisor/arch/x86/pci.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/hypervisor/arch/x86/pci.c b/hypervisor/arch/x86/pci.c
index 19d0ea9..86c5633 100644
--- a/hypervisor/arch/x86/pci.c
+++ b/hypervisor/arch/x86/pci.c
@@ -248,6 +248,13 @@ x86_pci_translate_msi(struct pci_device *device, unsigned int vector,
struct apic_irq_message irq_msg = { .valid = 0 };
unsigned int idx;

+ /*
+ * Ignore invalid target addresses, e.g. if the cell programmed the
+ * register to all-zero.
+ */
+ if (msi.native.address != MSI_ADDRESS_VALUE)
+ return irq_msg;
+
if (iommu_cell_emulates_ir(device->cell)) {
if (!msi.remap.remapped)
return irq_msg;
--
2.1.4

[Jan Kiszka]

The changes on x86 further improve assigning of PCI devices to non-root
cells and passing them back and forth.

The Orange Pi is much more stable now after enabling some Errata
workarounds in the kernel - only saw it crashing once since then. Ready
for playing with it seriously.

Jan

Jan Kiszka (6):
core: pci: Mask MSI-X vectors on reset also physically
inmates: arm: Allow to configure blinking LED via command line
arm/arm64: Consistently name CONFIG_MACH after the boards, not the
SoCs
configs, imates: Add support for Orange Pi Zero
x86: Expand x86_msi_vector to carry 64-bit address unconditionally
x86: Be graceful with invalid MSI target addresses

ci/jailhouse-config-banana-pi.h | 2 +-
configs/dts/inmate-orangepi0.dts | 108 ++++++++++++++++++++++++
configs/orangepi0-gic-demo.c | 63 ++++++++++++++
configs/orangepi0-linux-demo.c | 100 ++++++++++++++++++++++
configs/orangepi0.c | 148 +++++++++++++++++++++++++++++++++
hypervisor/arch/x86/include/asm/apic.h | 7 +-
hypervisor/arch/x86/pci.c | 15 +++-
hypervisor/pci.c | 8 +-
inmates/demos/arm/gic-demo.c | 23 ++---
inmates/lib/arm/include/mach.h | 15 +++-
inmates/lib/arm64/include/mach.h | 7 +-
11 files changed, 469 insertions(+), 27 deletions(-)

create mode 100644 configs/dts/inmate-orangepi0.dts
create mode 100644 configs/orangepi0-gic-demo.c
create mode 100644 configs/orangepi0-linux-demo.c
create mode 100644 configs/orangepi0.c

--
2.1.4

[Ralf Ramsauer]

Hi,

shouldn't we list the Orange Pi 0 in the supported boards section of
Readme.md?

Ralf

[Jan Kiszka]

On 2017-01-21 23:00, Ralf Ramsauer wrote:
> Hi,
>
> shouldn't we list the Orange Pi 0 in the supported boards section of
> Readme.md?

True, I'll add a corresponding line before applying to master.

Thanks,
Jan