Platform interrupts under AMD-Vi

[Valentine Sinitsyn]

Hi all,

Some background: AMD IOMMU specification provides way to specify that
given PCI device is permitted to send LINTx, INIT, NMI, ExtInt and
similar interrupts. It also defines an ACPI table which can be looked up
to check if given device can potentially assert these interrupts.

A quick question is: will I break anything in Jailhouse if I'll ignore
all of these and just disable platform interrupts for all PCI devices?
And does SMI require some special handling? (I remember there was a
discussion on that a long ago).

Thanks,
Valentine

[Jan Kiszka]

I suppose only SMIs may be relevant in practice, if at all only for
special on-chip devices. But SMIs we do not want anyway. Will probably
be an experiment...

Did you already parse the ACPI tables of your machines in this regard,
if there are suspicious patterns or of too many device just report most
of them? If there are recognizable patterns, we could at least issue
warnings during config generation.

Jan

--
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

[Valentine Sinitsyn]

On 09.02.2015 21:16, Jan Kiszka wrote:
> I suppose only SMIs may be relevant in practice, if at all only for
> special on-chip devices. But SMIs we do not want anyway. Will probably
> be an experiment...

Okay, thanks for the information.

> Did you already parse the ACPI tables of your machines in this regard,
> if there are suspicious patterns or of too many device just report most
> of them? If there are recognizable patterns, we could at least issue
> warnings during config generation.

The parser is in progress. A quick look at hexdump doesn't reveal
anything suspicious, but I'll have a look and write here if I'll find
anything interesting.

Valentine

[Valentine Sinitsyn]

On 09.02.2015 21:16, Jan Kiszka wrote:

> Did you already parse the ACPI tables of your machines in this regard,
> if there are suspicious patterns or of too many device just report most
> of them? If there are recognizable patterns, we could at least issue
> warnings during config generation.

My sample is not too exhaustive, but as far as my dev board is concerned
the only device permitted to issue platform interrupt in the ACPI table
is IOAPIC (which makes sense, as it can be programmed this way).

Looks like the correct pattern is to disable PMIs on all PCI devices,
but to enable everything for IOAPIC (can be restricted in a more
fine-grained way later, in ioapic_handle_access())

Valentine

[Jan Kiszka]

Platform interrupt == SMI? Note that we only allow fixed and low-prio
interrupts in vtd's iommu_map_interrupt. I would avoid deviating from
this for AMD unless the boards explode otherwise.

[Valentine Sinitsyn]

On 10.02.2015 01:49, Jan Kiszka wrote:
> Platform interrupt == SMI? Note that we only allow fixed and low-prio

All of them: SMI, LINTx, INIT, NMI, ExtInt (have I forgot anything)?

> interrupts in vtd's iommu_map_interrupt. I would avoid deviating from
> this for AMD unless the boards explode otherwise.

Agree, no need to deviate (I doubt anything will explode because of it).
So I'll just restrict all devices, including IOAPICs to fixed and
low-prio interrupts.

Valentine